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3.5 gsp s direct digital synthesizer with 12 - bit dac data sheet ad9914 rev. c document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2012C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features 3.5 gsps internal clock speed integrated 12 - bit dac frequency t uning resolution to 190 phz 16- bit phase tuning resolution 12- bit amplitude scaling programmable m odulus automatic linear and nonlinear frequency sweeping capability 32- bit p arallel datapath i nterface 8 frequency/phase offset profiles phase noise : ? 128 dbc/hz (1 khz o ffset at 1396 mhz ) wide band sfdr < ? 5 0 dbc serial or p arallel i/o control 1.8 v/3.3 v power supplies software and hardware controlled power - down 88- lead lfcsp package pll ref clk multiplier phase modulation capability amplitude modulation capability applications agile lo frequency synthesis programmable clock generator fm chirp source for radar and scanning systems test and measurement equipment acousto - optic device drivers polar m odulator fast f requency h opping functional block dia gram figure 1 . 12-bit dac 3.5gsps dds core timing and contro l 10836-001 ad9914 high speed parallel modulation port linear sweep block serial or parallel data port ref clk multiplier
ad9914 data sheet rev. c | page 2 of 48 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 general description ......................................................................... 3 specificat ions ..................................................................................... 4 dc specifications ......................................................................... 4 ac specifications .......................................................................... 5 absolute maximum ratings ............................................................ 8 thermal performance .................................................................. 8 esd caution .................................................................................. 8 pin configuration and function descriptions ............................. 9 typical performance characteristics ........................................... 12 equivalent circuits ......................................................................... 16 theory o f operation ...................................................................... 17 single tone mode ....................................................................... 17 profile modulation mode .......................................................... 17 digital ramp modulation mode .............................................. 17 parallel data port modulation mode ....................................... 17 prog rammable modulus mode ................................................. 17 mode priority .............................................................................. 18 functional block detail ................................................................. 19 dds core .................................................................................... 19 12- bit dac output .................................................................... 20 dac calibration output ........................................................... 20 reconstruction filter ................................................................. 20 clock input (ref_clk/ ref_clk ) ........................................ 21 pll lock indication .................................................................. 22 output shift keying (osk) ....................................................... 22 di gital ramp generator (drg) ............................................... 23 power - down control ................................................................ 27 programming and function pins ................................................. 28 serial programming ....................................................................... 31 control interface serial i/o ................................................... 31 general serial i/o operation ................................................... 31 instruction byte .......................................................................... 31 serial i/o port pin descriptions .............................................. 31 serial i/o timing diagrams ..................................................... 32 ms b/lsb transfers .................................................................... 32 parallel programming (8 - /16 - bit) ................................................ 33 register map and bit descriptions .............................................. 34 register bit descriptions ........................................................... 39 ou tline dimensions ....................................................................... 45 ordering guide .......................................................................... 45 revision history 11/13 rev. b to rev. c changes to table 2 ............................................................................. 5 change to programming and function pins section ................. 30 7/13 rev. a to rev. b change to cmos l ogic o utputs parameter, table 1 ................... 4 changes to table 2 ............................................................................. 7 changes to dds core section ....................................................... 19 changes to phase - locked loop (pll) multiplier section ........ 21 changed pll charge pump section to pll charge pump/ total feedback divider section; changes to table 8, pll loop filter components section, and fi gure 34 ........................ 22 change to table 14 .......................................................................... 34 changes to bits [15:8] , table 17 ..................................................... 42 8/ 12 rev. 0 to rev. a changes to features section ............................................................ 1 changed differential input voltage unit from mv p - p to v p - p .... 4 changes to tabl e 14 ....................................................................... 34 changes to tabl e 16 ....................................................................... 40 changes to tabl e 28 ....................................................................... 44 updated outline dimensions ....................................................... 45 7/12 revision 0: initial version
data sheet ad9914 rev. c | page 3 of 48 general description the ad9914 is a direct digital s ynthesizer (dds) feat uring a 12- bit d ac . the ad9914 uses advanced dds technology, coupled with an internal high speed, high performance dac to form a digitally programmable, complete high frequency synthesizer capable of generating a frequency - agile analog output sinusoidal wave form at up to 1.4 ghz. the ad9914 enables fast frequency hopping and fine tuning resolution ( 64- bit capable using programmable modulus mode). the ad9914 also offers fast phase and amplitude hopping capability. the frequency tuning and control words are loaded into the ad9914 via a serial or parallel i/o port. the ad9914 also supports a user defined linear sweep mode of operation for generating linear swept waveforms of frequency, phase , or amplitude. a hi gh speed , 32 - bit parallel data input port is included , enabling high data rates for polar modulation schemes and fast reprogramming of the phase, frequency , and amplitude tuning words. the ad991 4 is specified to operate over the extended industrial temperature range (see the absolute maximum ratings section ). figure 2 . detailed block di agram 10836-002 32 f0 t o f3 d0 t o d31 ps[2:0] i/o_upd a te power- down contro l ext_pwr_dwn dac_rset aout aout osk drover drctl drhold sync_clk a clock amplitude (a) frequenc y () phase () digi t a l ram p gener a t or 2 4 mu l tichi p synchroniz a tion sysclk pl l ref_clk ref_clk ad9914 output shift keying data route and partition control 3 internal clock timing and control acos (t + ) asin (t + ) sync_out sync_in loop_fi l ter master_reset dac 12-bit dds internal programming registers
ad9914 data sheet rev. c | page 4 of 48 specifications dc specifications avdd (1.8v) and dvdd (1.8v) = 1.8 v 5%, avdd (3.3v) and dvdd_i/o (3.3v) = 3.3 v 5%, t a = 25c, r set = 3.3 k?, i out = 20 ma, external reference clock frequency = 3.5 ghz with reference clock ( ref clk ) multiplier bypassed, unless otherwise noted. table 1. parameter min typ max unit test conditions/comments supply voltage dvdd_i/o 3.135 3.30 3.465 v pin 16, pin 83 dvdd 1.71 1.80 1.89 v pin 6, pin 23, pin 73 avdd ( 3.3v) 3.135 3.30 3.465 v pin 34, pin 36, pin 39, pin 40, pin 43, pin 47, pin 50, pin 52, pin 53, pin 60 avdd (1.8v) 1.71 1.80 1.89 v pin 32, pin 56, pin 57 supply current see also the total power dissipation specifications i dvdd_i/o 20 ma pin 16, pin 83 i dvdd 433 ma pin 6, pin 23, pin 73 i avdd ( 3 .3v) 640 ma pin 34, pin 36, pin 39, pin 40, pin 43, pin 47, pin 50, pin 52, pin 53, pin 60 i avdd (1.8v) 178 ma pin 32, pin 56, pin 57 total power dissipation base dds power, pll disabled 2392 3091 mw 3.5 ghz, single - tone mode, modules disabled, linear sweep disabled, amplitude scaler disabled base dds power, pll enabled 2237 2627 mw 2.5 ghz, single - tone mode, modules disabled, linear sweep disabled, amplitude scaler disabled linear sweep additional power 28 mw modulus additional power 20 mw amplitude scaler additional power 138 mw manual or a utomatic full power - down mode 400 616 mw using either the power - down and enable register or the ext_pwr_dwn pin cmos logic inputs input high voltage (v ih ) 2.0 dvdd_i/o v input low voltage (v il ) 0.8 v input current (i inh , i inl ) 60 200 a at v in = 0 v and v in = dvdd_i/o maximum input capacitance (c in ) 3 pf cmos logic outputs output high voltage (v oh ) 2.7 dvdd_i/o v i oh = 1 ma output low v oltage (v ol ) 0.4 v i ol = 1 m a ref clk input characteristics ref clk inputs should always be ac - coupled (both single - ended and differential) ref clk multiplier bypassed input capacitance 1 pf single - ended, each pin input resistance 1.4 k differential internally generated dc bias voltage 2 v differential input voltage 0.8 1.5 v p -p ref clk multiplier enabled input capacitance 1 pf single - ended, each pin input resistance 1.4 k differential internally generated dc bias voltage 2 v differential input voltage 0.8 1.5 v p -p
data sheet ad9914 rev. c | page 5 of 48 ac specifications avdd (1.8v) and dvdd (1.8v) = 1.8 v 5%, avdd 3 (3.3v) and dvdd_i/o (3.3v) = 3.3 v 5%, t a = 25c, r set = 3.3 k?, i out = 20 ma, external reference clock frequency = 3.5 ghz with reference clock ( ref clk ) multiplier bypassed , unless otherwise noted. table 2. parameter min typ max unit test conditions/comments ref clk input input f requency r ange ref clk multi plier bypassed input frequency range 5 00 3500 mhz maximum f out is 0.4 f sysclk duty cycle 45 55 % minimum differential input level 632 mv p - p equivalent to 316 mv swing on each leg system clock ( sysclk ) pll enabled vco frequency rang e 2400 2500 mhz vco gain (k v ) 6 0 mhz/v max imum pfd rate 125 mhz clock drivers sync_clk output driver frequency range 1 4 6 mhz duty cycle 45 50 55 % rise time/fall time (20% to 80%) 650 ps sync_out output driver 10 pf load frequency range 9.1 mhz duty cycle 33 66 % cfr2 register, bit 9 = 1 rise time (20% to 80%) 1350 ps 10 pf load fall time (20% to 80%) 1670 ps 10 pf load dac output characteristics output frequency range (1 st nyquist zone ) 0 1750 mhz output resistance 50 single - ended (each p in internally terminated to avdd (3.3 v ) ) output capacitance 1 pf full - scale output current 20.48 ma range depends on dac r set resistor gain error ? 10 +10 % fs output offset 0.6 a voltage compliance range avdd ? 0.50 avdd + 0.50 v wideband sfdr see the typical performance characteristics section 1 0 1 .1 mhz output ? 6 6 dbc 0 mhz to 1750 mhz 427.5 mhz output ? 6 5 dbc 0 mhz to 1750 mhz 696.5 mhz output ? 57 dbc 0 mhz to 1750 mhz 1396.5 mhz output ? 52 dbc 0 mhz to 1750 mhz narrow - band sfdr see the typical performance characteristics section 100.5 mhz output ? 95 dbc 50 0 khz 427.5 mhz output ? 95 dbc 500 khz 696.5 mhz output ? 95 dbc 500 khz 1396.5 mhz output ? 9 2 dbc 500 khz digital timing specifications time required to enter power - down 45 ns power - down mode l oses dac/pll c alibration settings time required to leave power - down 250 n s must re calibrate dac/pll minimum master reset time 24 sysclk cycles max imum dac calibration time (t cal ) 152 s f cal = f sysclk /384 usr 0 register, bit 6 = 0 ; s ee the dac calibration output section for formula maximum pll calibration time (t ref_clk ) 16 ms pfd rate = 25 mhz 8 ms pfd rate = 50 mhz maximum profile toggle rate 2 sync_clk period
ad9914 data sheet rev. c | page 6 of 48 parameter min typ max unit test conditions/comments parallel port timing write timing address setup time to wr active 1 ns address hold time to wr inactive 0 ns data setup time to wr inactive 3.8 ns data hold time to wr inactive 0 ns wr minimum low time 2.1 ns wr minimum high time 3.8 ns minimum wr time 10.5 ns read timing address to data valid 92 ns address hold to rd inactive 0 ns rd active to data valid 69 ns rd inactive to data tristate 50 ns rd minimum low time 69 ns rd minimum high time 50 ns serial port timing sclk clock rate (1/t clk ) 80 mhz sclk d uty c ycle = 50% sclk pulse w i dth high, t high 1.5 n s sclk pulse width low, t low 5.1 ns sdio to sclk setup time, t ds 4.9 ns sdio to sclk hold time, t dh 0 ns sclk falling edge to valid data on sdio/sdo, t dv 78 ns cs to sclk setup time, t s 4 ns cs to sclk hold time, t h 0 ns cs minimum pulse width high, t pwh 4 ns data port timing d[31:0] setup time to sync_clk 2 ns d[31:0] hold time to sync_clk 0 ns f[3:0] setup time to sync_clk 2 ns f[3:0] hold time to sync_clk 0 ns io_update pin setup time to sync_clk 2 ns io_update pin hold time to sync_clk 0 ns profile pin setup time to sync_clk 2 ns profile pin hold time to sync_clk 0 ns dr_ctl/dr_hold setup time to sync_clk 2 ns dr_ctl/dr_hold hold time to sync_clk 0 ns
data sheet ad9914 rev. c | page 7 of 48 parameter min typ max unit test conditions/comments data latency (pipeline delay) sysclk cycles = f s = system clock frequency in ghz single tone mode or profile mode ( matched latency disabled ) frequency 3 18 sysclk cycles osk disabled 342 sysclk cycles osk enabled phase 294 sysclk cycles osk disabled 318 sysclk cycles osk enabled amplitude 1 02 sysclk cycles osk en abled single tone mode or profile mode ( matched latency enabled ) frequency 3 18 sysclk cycles osk disabled 342 sysclk cycles osk en abled phase 3 18 sysclk cycles osk disabled 342 sysclk cycles osk en abled amplitude 3 42 sysclk cycles osk en abled modulation mode with 32 - bit parallel port (matched latency disabled) frequency 318 sysclk cycles osk disabled 342 sysclk cycles osk enabled phase 2 94 sysclk cycles osk disabled 318 sysclk cycles osk enabled amplitude 102 sysclk cycles osk enabled modulation mode with 32 - bit parallel port (matched latency enabled) frequency 318 sysclk cycles osk disabled 342 sysclk cycles osk enabled phase 318 sysclk cycles osk disabled 342 sysclk cycles osk enabled amplitude 342 sysclk cycles osk enabled sweep mode ( match latency disabled ) frequency 3 42 sysclk cycles osk disabled 366 sysclk cycles osk enabled phase 3 1 8 sysclk cycles osk disabled 342 sysclk cycles osk enabled amplitude 1 26 sysclk cycles osk en abled sweep mode ( match latency enabled ) frequency 342 sysclk cycles osk disabled 366 sysclk cycles osk enabled phase 342 sysclk cycles osk disabled 366 sysclk cycles osk enabled amplitude 366 sysclk cycles osk en abled
ad9914 data sheet rev. c | page 8 of 48 absolute maximum ratings table 3. parameter rating avdd (1.8 v), dvdd (1.8 v) supplies 2 v avdd (3.3 v), dvdd_i/o (3.3 v) supplies 4 v digital input voltage ?0.7 v to +4 v digital output current 5 ma storage temperature range ?65c to +150c operating temperature range ?40c to +85c maximum junction temperature 150c lead temperature (10 sec soldering) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal performance table 4. symbol description value 1 unit ? ja junction-to-ambient thermal resistance (still air) per jedec jesd51-2 24.1 c/w ? jma junction-to-ambient thermal resistance (1.0 m/sec airflow) per jedec jesd51-6 21.3 c/w ? jma junction-to-ambient thermal resistance (2.0 m/sec air flow) per jedec jesd51-6 20.0 c/w ? jb junction-to-board thermal resistance (still air) per jedec jesd51-8 13.3 c/w ? jb junction-to-board characterization parameter (still air) per jedec jesd51-6 12.8 c/w ? jc junction-to-case thermal resistance 2.21 c/w ? jt junction-to-top-of-package characterization parameter (still air) per jedec jesd51-2 0.23 c/w 1 results are from simulations. pcb is jedec multilayer. thermal performance for actual applications re quires careful inspection of the conditions in the application to determine if they are similar to those assumed in these calculations. esd caution
data sheet ad9914 rev. c | page 9 of 48 pin configuration an d function descripti ons figure 3 . pin configuration table 5. pin function descriptions pin no. mnemonic i/o 1 description 1, 2, 13 to 15, 68 to 72, 75 to 81, 87, 88 d 5 to d7, d16 to d31, d27 to d31 i /o parallel port pins. the 32- bit parallel port offers the option for serial or parallel programming of the internal registers . in addition, the parallel port can be configured to provide direct fsk, psk , or ask (or combinations thereof ) modulation data. the 32- bit parallel port configuration is set by the state of the four f unction pins (f0 to f3). 3 d1 5/a 7 i /o parallel port pin /address line . the state of the f0 to f3 function pins deter mine s if this pin acts as a line for direct fsk, psk, or ask data or as an address line for programming the internal registers . 4 d14/a6 i/o parallel port pin /address line . the state of the f0 to f3 function pins determines if this pin acts as a line for direct fsk, psk, or ask data or as an address line for programming the internal registers. 5 d13/a5 i/o parallel port pin / address line. the state of the f0 to f3 function pins determines if this pin acts as a line for direct fsk, psk, or ask data or as an address line for programming the internal registers. 8 d12/a4 i/o parallel port pin /address line . the state of the f0 to f3 function pins determines if this pin acts as a line for direct fsk, psk, or ask data or as an address line for programming the internal registers. 9 d11/a3 i/o parallel port pin /address line . the state of the f0 to f3 function pins determines if this pin acts as a line for direct fsk, psk, or ask data or as an address line for programming the internal registers. 10 d10/a2 i/o parallel port pin /address line . multipurpose pin depending on the state of the function pins (f0 to f3). the state of the f0 to f3 function pins determines if this pin acts as a line for direct fsk, psk, or ask data or as an address line for programming the internal registers. 11 d9/a1 i/o parallel port pin / a ddress line . multipurpose pin depending on the state of the function pins (f0 to f3). the state of the f0 to f3 function pins determines if this pin acts as a line for direct fsk, psk, or ask data or as an address line for programming the internal registers. 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 d17 d16 d15/a7 d14/a6 d13/a5 dvdd (1.8v) dgnd d12/a4 d 1 1/a3 d10/a2 d9/a1 d8/a0 d7 d6 d5 dvdd_i/o (3.3v) 17 dgnd 18 d4/syncio 19 d3/sdo 20 d2/sdio/wr 23 24 25 26 27 28 29 30 31 32 33 34 36 37 dvdd (1.8v) dgnd ps0 ps1 ps2 f0 f1 f2 f3 a vdd (1.8v) agnd a vdd (3.3v) 35 agnd a vdd (3.3v) agnd 38 agnd 39 a vdd (3.3v) 40 a vdd (3.3v) 41 aout 58 57 56 55 54 53 52 51 50 49 48 47 46 45 loop_fi l ter 59 ref 60 a vdd (3.3v) 61 sync_out 62 sync_in 63 drct l 64 drhold 65 drover 66 osk a vdd (1.8v) a vdd (1.8v) ref clk ref clk a vdd (3.3v) a vdd (3.3v) agnd a vdd (3.3v) agnd dac_rset a vdd (3.3v) agnd dac_b p 78 77 76 75 74 73 72 71 70 69 68 67 d23 79 d22 80 d21 81 d20 82 sync_clk 83 dvdd_i/o (3.3v) 84 dgnd 85 master_reset 86 i/o_upd a te 87 d19 88 d18 d24 d25 d26 dgnd dvdd (1.8v) d27 d28 d29 d30 d31 ext_pwr_dwn notes 1. the epad must be soldered to ground. 10836-003 21 d1/sclk/rd 22 d0/cs/pwd 42 aout 43 a vdd (3.3v) 44 agnd ad9914 t o p view (not to scale)
ad9914 data sheet rev. c | page 10 of 48 pin no. mnemonic i/o 1 description 12 d8/a0 i/o parallel port pin /address line . t he state of the f0 to f3 function pins determines if this pin acts as a line for direct fsk, psk, or ask data or as an address line for programming the internal registers. 18 d4/syncio i parallel port pin/ serial port synchronization pin. this pin is d4 for direct fsk, psk, or ask data. if serial mode is invoked via f0 to f3 , this pin is used to reset the serial port. 19 d3/sdo i/o parallel port pin/serial data output . this pin is d3 for direct fsk, psk, or ask data. if serial mode is invoked via f0 to f3, this pin is used for read back mode for serial operation. 20 d2/sdio/ wr i/o parallel port pin/serial data input and ou t put/ write input . this pin is d2 for direct fsk, psk, or ask data. if serial mode is invoked via f0 to f3 , this pin is used for the sdio for serial operation. if parallel mode is enabled, this pin is used to write to change the values of the internal registers. 21 d1/sclk/ rd i parallel port pin/serial clock/read input. this pin is d1 for di rect fsk, psk, or ask data. if serial mode is invoked via f0 to f3, this pin is used for sclk for serial operation. if parallel mode is enabled, this pin is used to read back the value of the internal registers. 22 d0/ cs / pwd i parallel port pin/chip select/ parallel width. this pin is d0 for direct fsk, psk, or ask data. if serial mode is invoked via f0 to f3 , this pin is used for the c hip s el ect for serial operation. if parallel mode is enabled, this pin is used to set either 8- bit data or 16- bit data. 6, 23, 73 dvdd (1.8v) i digital core supplies ( 1.8 v ) . 7, 17, 24, 74, 84 dgnd i digital ground. 16, 83 dvdd_i/o (3.3v) i digital input/output supplies ( 3.3 v ). 32, 56, 57 avdd (1.8v) i analog core supplies ( 1.8 v ). 33, 35, 37, 38, 44, 46, 49, 51 agnd i analog ground. 34, 36, 39, 40, 43, 47, 50, 52, 53, 60 avdd (3.3v) i analog dac supplies ( 3.3 v ) . 25, 26, 27 p s0 to ps2 i profile select pins. digital inputs (active high). use these pins to select one of eight phase/frequency profiles for the dds. changing the state of one of these pins transfers the current contents of all i/o buffers to the corresponding registers. state changes should be set up on the sync_clk pin (pin 82) . 28, 29, 30, 31 f0 to f3 i function pins. digital i nputs. the state of these pins determine s if a serial or parallel interface is used. in addition, the function pins determine how the 32 - bit parallel data - word is partition ed for fsk, psk, or ask modulation mode. 41 aout o dac complementary outpu t source. analog output (voltage mode). internally c onnect ed through a 50 resistor to avdd (3.3v) . 42 a ou t o dac outp ut source. analog output (vol t age mode). internally c onnect ed through a 50 resistor to avdd (3.3v) . 45 dac_bp i dac bypass pin. provides access to the common control node of the dac current sources. connecting a capacitor between this pin and ground can improve noise performance at the dac output. 48 dac_rset o analog reference. this pin programs the dac output full - scale referenc e cu rrent. connect a 3.3 k resistor to agnd. 54 ref_clk i complementary reference clock input. analog input. 55 ref_clk i reference clock input. analog input. 58 loop_ filter o external pll loop filter node . 59 ref o local pll reference supply . typically at 2.05 v. 61 sync_out o digital synchronization output. used to s ynchronize multiple chips. 62 sync_in i digital synchronization input. used to s ynchronize multiple chips. 63 dr ctl i ramp control. digital input (active high ). this pin controls the sweep direction (up/down). 64 dr hold i ramp hold. digital input (active high ). pauses the sweep when active. 65 dr over o ramp over. digital output (active high ). this pin switches to logic 1 when the digital ramp generator reaches its programmed upper or lower limit. 66 osk i output shift keying. digital input (active high). when the osk features are placed in either manual or automatic mode, this pin controls the osk function. in manual mode, it toggles the multiplier betw een 0 (low) and the programmed amplitude scale factor (high). in automatic mode, a low sweeps the amplitude down to zero and a high sweeps the amplitude up to the amplitude scale factor.
data sheet ad9914 rev. c | page 11 of 48 pin no. mnemonic i/o 1 description 67 ext_pwr_dwn i external power - down. digital input (active high ). a high level on this pin initiates the curren tly programmed power - down mode. 82 sync_clk o clock output . digital output. many of the digital inputs on the chip, such as i/o_update, p s [2:0], and the p arallel data p ort (d0 to d31) , must be set up on the risi ng edge of this signal. 85 master_reset i master reset. digital input (active high ). clears all memory elements and sets registers to default values. 86 i/o_update i input/output update. digital input (active high). a high on this pin transfers the contents of the i/o buffers to the corresponding internal registers. epad exposed pad. the epad must be soldered to ground. 1 i = input, o = output.
ad9914 data sheet rev. c | page 12 of 48 typical performance characteristics n ominal supply voltage; dac r set = 3.3 k , t a = 25 c , unless otherwise noted. figure 4 . wide b and sfdr at 171.5 mhz sysclk = 3.5 ghz (sysclk pll bypassed) figure 5 . wide b and sfdr at 427.5 mhz sysclk = 3.5 ghz (sysclk pll bypassed) figure 6 . wide b a nd sfdr at 696.5 mhz, sysclk = 3.5 ghz (sysclk pll bypassed) figure 7 . narrow - b a nd sfdr at 171.5 mhz, sysclk = 3.5 ghz (sysclk pll bypassed) figure 8 . narrow - b an d sfdr at 427.5 mhz, sysclk = 3.5 ghz (sysclk pll bypassed) figure 9 . narrow - b and sf dr at 696.5 mhz, sysclk = 3.5 ghz (sysclk pll bypassed) start 0hz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 175mhz/div stop 1.75ghz sfdr (dbc) 10836-004 start 0hz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 175mhz/div stop 1.75ghz sfdr (dbc) 10836-005 start 0hz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 175mhz/div stop 1.75ghz sfdr (dbc) 10836-006 center 171.5mhz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 50khz/div span 500khz sfdr (dbc) 10836-007 center 427.5mhz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 50khz/div span 500khz sfdr (dbc) 10836-008 center 696.5mhz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 50khz/div span 500khz sfdr (dbc) 10836-009
data sheet ad9914 rev. c | page 13 of 48 figure 10 . wide b a nd sfdr at 1396.5 mhz, sysclk = 3.5 ghz (sysclk pll bypassed) figure 11 . wide b an d sfdr vs. normalized f out sysclk = 3.5 g hz figure 12 . wideb and sfdr vs. normalized f out , sysclk = 2.5 ghz to 3.5 ghz figure 13 . narrow - b and sfdr at 1396.5 mhz, sysclk = 3.5 ghz (sysclk pll bypassed) figure 14 . absolute phase noise of ref clk source driving ad9914 rohde & schwarz sma100 signal generator at 3.5 ghz buffered by series adclk925 figure 15 . absolu te phase noise curves of dds output at 3.5 g hz operation ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 sfdr (dbc) start 0hz 175mhz/div stop 1.75ghz 10836-010 0 ?80 0 0.05 0.10 0.15 0.40 0.35 0.30 0.25 0.20 sfdr (dbc) f c / f s ?70 ?60 ?50 ?40 ?30 ?20 ?10 10836-0 1 1 0 ?80 0 0.05 0.10 0.15 0.40 0.35 0.30 0.25 0.20 sfdr (dbc) f c / f s ?70 ?60 ?50 ?40 ?30 ?20 ?10 10836-012 sysclk = 2.7ghz sysclk = 2.8ghz sysclk = 2.9ghz sysclk = 3.0ghz sysclk = 3.1ghz sysclk = 3.2ghz sysclk = 3.3ghz sysclk = 3.4ghz sysclk = 3.5ghz sysclk = 1.5ghz sysclk = 1.6ghz sysclk = 1.7ghz sysclk = 1.8ghz sysclk = 1.9ghz sysclk = 2.0ghz sysclk = 2.1ghz sysclk = 2.2ghz sysclk = 2.3ghz sysclk = 2.4ghz sysclk = 2.5ghz sysclk = 2.6ghz center 1396.5mhz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 50khz/div span 500khz sfdr (dbc) 10836-013 10 100 1k 10k 100k 1m 10m 100m frequency offset (hz) ?70 ?90 ?80 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 phase noise (dbc/hz) sma sma and adclk925 10836-014 10 100 1k 10k 100k 1m 10m 100m frequency offset (hz) ?70 ?90 ?80 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 phase noise (dbc/hz) 1396mhz 696mhz 427mhz 171mhz 10836-015
ad9914 data sheet rev. c | page 14 of 48 figure 16 . absolu te phase noise curves of normalized ref clk source to dds output at 1396 mhz (sysclk = 3.5 ghz) figure 17 . residual phase noise curves figure 18 . power supply current vs. sysclk figure 19 . absolute phase noise curves of dds output using internal pll at 2.5 ghz operation figure 20 . residual pn vs . absolute pn measurement curves at 1396 mhz figure 21 . residual phase noise vs. normalized absolute ref clk source phase noise at 1396 mhz 10 100 1k 10k 100k 1m 10m 100m frequency offset (hz) ?70 ?90 ?80 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 phase noise (dbc/hz) 1396mhz normalized ref clk source 10836-016 ?60 ?90 ?80 ?70 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 ?180 10836-017 10 100 1k 10k 100k 1m 10m 100m frequency offset (hz) phase noise (dbc/hz) 427mhz 1396mhz 696mhz 171mhz 0.5 0.4 0.3 0.2 0.1 0 500 1000 4000 3500 3000 2500 2000 1500 supply current (a) system clock (mhz) 10836-018 3.3v analog 3.3v digital 1.8v analog 1.8v digital 10 100 1k 10k 100k 1m 10m 100m frequency offset (hz) ?70 ?90 ?80 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 phase noise (dbc/hz) 978mhz 305mhz 123mhz 497mhz 10836-019 10 100 1k 10k 100k 1m 10m 100m frequency offset (hz) phase noise (dbc/hz) 1396mhz absolute 1396mhz residua l ?60 ?90 ?80 ?70 ?100 ?110 ?120 ?130 ?140 ?150 ?160 10836-020 ?60 ?90 ?80 ?70 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 ?180 10 100 1k 10k 100k 1m 10m 100m frequency offset (hz) phase noise (dbc/hz) 1396mhz absolute 1396mhz residua l 10836-021
data sheet ad9914 rev. c | page 15 of 48 figure 22 . sync_out ( f sysclk /384) figure 23 . dac calibration time v s. sysclk rate . see the dac calibration output section for formula . figure 24 . measured rising linear frequency sweep figure 25 . measured falling linear frequency sweep 10836-022 ch2 1.0v ? m20.00ms it 40.0ps/pt a ch2 1.64v 1 2.0 1.8 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 500 3500 time (ms) system clock rate (mhz) 1000 1500 2000 2500 3000 10836-023 930 870 880 890 900 910 920 ?6 ?2 ?4 6 4 2 0 frequency (mhz) time (ms) 10836-024 930 870 880 890 900 910 920 ?6 ?2 ?4 6 4 2 0 frequency (mhz) time (ms) 10836-025
ad9914 data sheet rev. c | page 16 of 48 equivalent circuits figure 26 . dac output figure 27 . ref clk input figure 28 . cmos input figure 29 . cmos output 10836-044 switch control code agnd avdd (3.3v) current switch array current switch array aout aout internal 50? internal 50? i fs /2 + i code i fs /2 ? i code i fs 41 42 10836-048 ref_clk ref_clk avdd (3.3v) dvdd (3.3v) 10836-045 dvdd (3.3v) 10836-043
data sheet ad9914 rev. c | page 17 of 48 theory of operation the ad9914 has five modes of operation. ? single tone ? profile m odulation ? digital ramp modulation (linear sweep) ? parallel data port modulation ? programmable m odulus mode the modes define the data source used to supply the dds with its signal control paramet ers: frequency, phase, or ampli tude. the partitioning of the data into different combinations of frequency, phase, and amplitude is established based on the mode and/or specific control bits and function pins . although the various modes are described independe ntly, they can be enabled simultaneously. this provides an unprecedented level of flexibility for generating complex modulation schemes. however, to avoid multiple data sources from driving the same dds signal control parameter, the device has a built - in p riority protocol. in single tone mode, the dds signal control parameters come directly from the profile programming registers. in digital ramp modulation mode, the dds signal control parameters are delivered by a digital ramp generator. in parallel data po rt modulation mode, the dds signal control parameters are driven directly into the parallel port. the various modulation modes generally operate on only one of the dds signal control parameters (two in the case of the polar modulation format via the parall el data port ). the unmodulated dds signal control parameters are stored in programming registers and automatically route d to the dds based on the selected mode. a separate output shift keying (osk) function is also available. this function employs a separa te digital linear ramp generator that affects only the amplitude parameter of the dds. the osk function has priority over the other data sources that can drive the dds amplitude parameter. as such, no other data source can drive the dds amplitude when the osk function is enabled. single tone mode in single tone mode, the dds signal control parameters are supplied directly from the profile programming registers. a profile is an independent register that contains the dds signal control parameters. eight profile registers are available. note that the profile pins must be used to select the desired register . profile m o dulation mode each profile is independently accessible. for fsk, psk, or ask modulation, use the three external profile pins (p s [2:0]) to select the desired profile. a change in the state of the profile pins with the next rising edge on sync_clk updates t he dds with the parameters specified by the selected profile. therefore , the profile change must meet the setup and hold times to the sync_clk rising edge. note that amplitude control must also be enabled using the osk enable bit in the cfr1 register ( 0x00 [ 8]) . digital ramp modulat ion mode in digital ramp modulation mode, the modulated dds signal control parameter is supplied directly from the digital ramp generator (drg). the ramp generation parameters are controlled through the serial or parallel i/o port. the ramp generation parameters allow the user to control both the rising and falling slopes of the ramp. the upper and lower boundaries of the ramp, the step size and step rate of the rising portion of the ramp, and the step size and step rate o f the falling portion of the ramp are all programmable. the ramp is digitally generated with 32 - bit output resolution. the 32 - bit output of the drg can be programmed to affect frequency, phase, or amplitude. when programmed for frequency, all 32 bits are used. however, when programmed for phase or a mplitude, only the 16 msbs or 12 msbs, respectively, are used. the ramp direction (rising or falling) is externally controlled by the drctl pin. an additional pin (drhold) allows the user to suspend the ramp generator in its present state. note that amplitude control must also be enabled using the osk enable bit in register cfr1 . parallel data port m odulation mode in parallel data port modulation mode, the modulated dds signal control parameter(s) a re supplied directly from the 32 - bit parallel data port. the f unction pins de fine how the 32 - bit data - word is applied to the dds signal control parameters. format ting of the 32 - bit data - word is unsigned binary, regardless of the destination. parallel data clock (sync_ clk) the ad9914 generates a clock signal on the sync_ cl k pin that runs at 1/24 of the dac sample rate (the sample rate of the par allel data port). sync_ clk serves as a data clock for the parallel port. programmable modulus mode in programmable modulus mode, the drg is used as an auxiliary accumulator to alter the frequency equation of the dds core, making it possible to implement fractions that are not r estricted to a power of 2 in the denominator. a standard dds is restricted to powers of 2 as a denominator because the phase accumulator is a set of bits as wide as the frequency tuning word (ftw). when in programmable modulus mode, however, the frequency equation is: f 0 = (f s )( ftw + a / b )/2 32 where f 0 / f s < ?, 0 ftw < 2 31 , 2 b 2 32 C 1, and a < b . this equation implies a modulus of b 2 32 (rather than 2 32 , in the case of a standard dds). furthermore , because b is programmable, the result is a dds with a programmable modulus.
ad9914 data sheet rev. c | page 18 of 48 when in programmable modulus mode, the 32 - bit auxiliary accumulator operates in a way that allows it to roll over at a value other than its full capacity of 2 32 . that is, it operates with a modified modulus based on the programmabl e value of b. with each roll over of the auxiliary accumulator, a value of 1 lsb adds to the current accumulated value of the 32 - bit phase accumulator. this behavior changes the modulus of the phase accumulator to b 2 32 (instead of 2 32 ) , allowing it to synthesize the desired f 0 . to determine the programmable modulus mode register values for ftw, a, and b , the user must first define f 0 / f s as a ratio of relatively prime integers, m/n. that is, having converted f 0 and f s to integers , m and n , reduce the fraction, m/n, to its lowest terms. then, divide m 232 by n. the integer part of this division operation is the value of ftw (register 0x04[31:0]). the remainder, y , of this division operation is y = (2 32 m ) C ( ftw n ) the value of y faci litates the determination of a and b by taking the fraction, y/n, and reducing it to its lowest terms. then, the numerator of the reduced fraction is a (register 0x06[31:0]) and the denominator is the b (register 0x05[31:0]). for example, synthesizing prec isely 300 mhz with a 1 ghz system clock is not possible with a standard dds. it is possible, however, using programmable modulus as follows. first, express f 0 / f s as a ratio of integ ers: 300,000,000/1,000,000,000 reducing this fraction to lowest terms yiel ds 3/10 ; therefore , m = 3 and n = 10. ftw is the integer part of (m 2 32 )/n, or (3 2 32 )/10, which is 1,288,490,188 ( 0x 4ccccccc in 32 - bit hexadecimal notation). the remainder, y, of (3 2 32 )/10, is (2 32 3) ? (1,288,490,188 10), which is 8 . therefore, y/n is 8/10, which reduces to 4/5. therefore, a = 4 and b = 5 ( 0x 00000004 and 0x 00000005 in 32 - bit hexadecimal notation, respectively). programming the ad9914 with these values of ftw , a, and b result s in an output frequency that is exactly 3/10 of the system clock frequency. mode priority the ability to activate each mode independently makes it possible to have multiple data sources attempting to drive the same dds signal control parameter (frequency, phase, and amplitude) . to avoid contention, the ad9914 has a built - in priority system. table 6 summarizes the priori ty for each of the dds modes . the data source column in table 6 list s data sour ces for a particu lar dds signal con trol parameter in descending order of precedenc e. for example, if the profile mode enable bit and the parallel data port enable bit (0x01[23:22]) are set to logic 1 and both are programmed to source the frequency tuning word to dds output, the profile modulation mode has priority over the parallel data port modulation mode . table 6. data source priority priority dds signal control parameters data source conditions highest priority programmable modulus if programmable modulus mode is used to output frequency only, no other data source can be used to control the output frequency in this mode. note that the drg is used in conjunction with programmable modulus mode; therefore, the drg cannot be used to sweep phase or amplitude in programmable modulus mode. if output phase offset control is desired, enable profile mode and use the profile registers and profile pins accord ingly to control output phase adjustment. if output amplitude control is desired, enable profile mode and use the profile registers and profile pins accordingly to control output amplitude adjustment. note that the osk enable bit must be set to control the output amplitude. drg the digital ramp modulation mode is the next highest priority mode. if the drg is enabled to sweep output frequency, phase, or amplitude, the two parameters not being swept can be controlled independently via the profile mode. profiles the profile modulation mode is the next highest priority mode. profile mode can be used to control all three parameters independently, if desired. lowest priority parallel port parallel data port modulation has the lowest priority but the most flexibility as far as changing any parameter at the high rate. see the programming and function p ins section.
data sheet ad9914 rev. c | page 19 of 48 functional block det ail dds core the direct digital synthesizer (dds) block generates a reference signal (sine or cosine based on 0x00 [16], the enable sine output bit). the parameters of the reference signal (frequency, phase, and amplitude) are applied to the dds at its frequency, phase offset, and amplitude control inputs, as shown in figure 30. the output frequency (f out ) of the ad9914 is controlled by the frequency tuning word (ftw) at the frequency control input to the dds. the relationshi p among f out , ftw, and f sysclk is given by sysclk out f ftw f ? ? ? ? ? ? = 32 2 (1) w here ftw is a 32 - bit integer ranging in value from 0 to 2,147,483,647 (2 31 ? 1), which represents the lower half of the full 32 - bit range. this range constitutes frequencies from dc to nyquist (that is, ? f sysclk ). the ftw required to generate a desired value of f out is found by solving equation 1 for ftw, as given in equation 2. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = sysclk out f f ftw 32 2 round (2) where the round( x ) function rounds the argument (the value of x) to the nearest in teger. this is required because the ftw is constrained to be an integer value. for example, for f out = 41 mhz and f sysclk = 122.88 mhz, ftw = 1,433,053,867 (0x556aaaab). programming an ftw greater than 2 31 produces an aliased image that appears at a freque ncy given by sysclk out f ftw f ? ? ? ? ? ? ? = 32 2 1 (for ftw 2 31 ) the relative phase of the dds signal can be digitally controlled by means of a 16 - bit phase offset word (pow). the phase offset is applied prior to the angle - to - amplitude conversion block internal to the dds core. the relative phase offset ( ) is given by ? ? ? ? ? ? ? ? ? ? ? ? = ? 14 14 2 360 2 2 pow pow where the upper quantity is for the phase offset expressed as radian units and the lower quantity as degrees. to find the pow value necessary to develop an arbitrary , solve the preceding equation for pow and round the result (in a manner similar to that described previously for finding an arbitrary ftw). the relative amplitude of the dds signal can be digitally scaled (relative to full scale) by means of a 12 - bit ampl itude scale factor (asf). the amplitude scale value is applied at the output of the angle - to - amplitude conversion block internal to the dds core. the amplitude scale is given by ? ? ? ? ? ? = 12 12 2 log 20 2 asf asf scale amplitude (3) where the upper quantity is amplitude expressed as a fraction of full scale and the lower quantity is expressed in decibels relative to full scale. to find the asf value necessary for a particular scale factor, solve equation 3 fo r asf and round the result (in a manner similar to that described previousl y for finding an arbitrary ftw). when the ad9914 is programmed to modulate any of the dds signal control parameters, the max imum modulation sample rate is 1/24 f sysclk . this means that the modulation signal e xhibits images at multiples of 1/24 f sy sclk . the impact of these images must be considered when using the device as a modulator. figure 30 . dds block diagram dds_clk 32 17 frequenc y contro l angle- t o- amplitude conversion (sine or cosine) phase offset contro l t o dac (msbs) d q r accumul a t or reset 32 16 msb aligned amplitude control 12 dds signa l contro l p arameters 14 12 17 32 32 12 12 32-bit accumul a t or 10836-026
ad9914 data sheet rev. c | page 20 of 48 12- bit dac output the ad9914 incorporates an integrated 12 - bit, current output dac. the output current is delivered as a balanced signal using two outputs. the use of b alanced outputs reduces the potential amount of common - mode noise present at the dac output, offering the advantage of an increased signal - to - noise ratio. an external resistor (r set ) connected between the dac_rset pin and agnd establishes the reference cur rent. the recommended value of r set is 3.3 k?. attention should be paid to the load termination to keep the output voltage within the specified compliance range; voltages developed beyond this range cause excessive distortion and can damage the dac output circuitry. dac c alibration output the dac cal enable bit in the cfr4 c o ntrol register (0x03[ 24] ) must be manually set an d then cleared after each power - up and every time the ref clk or internal system clock is changed. this initiate s an internal calibration routine to optimize the setup and hold time s for internal dac timing. failure to calibrate may degrade performance and even result in loss of functionality . the length of time to calibrate the dac c lock is calculated from the following equation: s s cal f f t 840 , 531 ) ( = reconstruction filte r the dac output signal appears as a sinusoid sampled at f s . the frequency of the sinusoid is determined by the frequency tuning word (ftw) that appears at the input to the dds. the dac output is typically passed through an external reconstruction filter tha t serves to remove the artifacts of the sampling process and other spurs outside the filter bandwidth. because the dac constitutes a sampled system, its output must be filtered so that the analog waveform accurately represents the digital samples supplied to the dac input. the unfiltered dac output contains the desired baseband signal, which extends from dc to the nyquist frequency (f s /2). it also contains images of the baseband signal that theoretically extend to infinity . notice that the odd numbered ima ges (shown in figure 31 ) are mirror images of the baseband signal. furthermore, the entire dac output spectrum is affected by a sin(x)/x response, which is caused by the sample - and - hold nature of the dac output signal. for applications using the fundamental frequency of the dac output, the response of the reconstruction filter should preserve the baseband signal (image 0), while completely rejecting all other images. however, a practical filter implementation typically exhibits a relatively flat pass band that covers the desired output frequency plus 20%, rolls off as steeply as possible, and then maintains significant (though not complete) rejection of the remaining i mages. depending on how close unwanted spurs are to the desired signal, a third - , fifth - , or seventh - order elliptic low - pass filter is common. some applications operate from an image above the nyquist frequency, and those applications use a band - pass filte r instead of a low - pass filter. the design of the reconstruction filter has a significant impact on the overall signal performance. therefore, good filter design and implementation techniques are important for obtaining the best possible jitter results. figure 31 . dac spectrum vs. reconstruction filter response primary signal filter response sin(x)/x envelope spurs image 0 image 1 image 2 image 3 image 4 0 ?20 ?40 ?60 ?80 ?100 magnitude (db) f s /2 f s 3 f s /2 2 f s 5 f s /2 f base band 10836-027
data sheet ad9914 rev. c | page 21 of 48 clock input (ref_clk / ref_clk ) ref_clk/ ref_clk overview the ad9914 supports a number of options for producing the internal sysclk signal (that is, the dac sample clock) via the ref_clk/ ref_clk input pins. the ref_clk input can be driven directly from a di ffe rential or single - ended source. there is also an internal phase - locked loop (pll) multiplier that can be independently enabled. however, the pll limits the sysclk signal between 2.4 ghz and 2.5 ghz operation. a differential signal is recommended when th e pll is bypassed. a block diagram of the ref_clk functionality is shown in figure 32. figure 32 also shows how the cfr3 control bits are associated with specific functional blocks. figure 32 . ref_clk block diagram the pll enable bit is used to choose between the pll path or the direct input path. when the direct input path is selected, the ref_clk/ ref_clk pins must be driven by an external signal source (single - ended or differential). input frequencies up to 3.5 ghz are supported. direct driven ref_clk/ ref_clk with a differential signal source, the ref_clk/ ref_clk pins are driven with complementary signals and ac - coupled with 0.1 f capacitors. with a single - ended signal source, either a single - ended - to - differential conv ersion can be employed or the ref_clk input can be driven single - ended directly. in either case, 0.1 f capacitors are used to ac couple both ref_clk/ ref_clk pins to avoid disturbing the internal dc bias voltage of ~1.35 v. see figure 33 for more details. the ref_clk/ ref_clk input resistance is ~2.5 k? differential (~1.2 k? single - ended). most signal sources have relatively low outp ut impedances. the ref_clk/ ref_clk input resistance is relatively high; therefore, its effect on the termination impedance is negligible and can usually be chosen to be the same as the output impedance of the signal source. the bottom two examples in figure 33 assume a signal source with a 50 ? output impedance. figure 33 . direct connection diagram phase - locked loop (pll ) multiplier an internal phase - locked loop (pll) provides the option to use a reference clock frequency that is significantly lower than th e system clock frequency. the pll supports a wide range of programmable even frequency multiplica tion factors ( 2 0 t o 510 ) as well as a programmable charge pump current and external loop filter components (connected via the pll loop_filter pin). these features add an extra layer of flexibility to the pll, allowing optimization of phase noise performance and flexibility in frequency plan develop ment. the pll is also equipped with a pll lock bit indicator (0x1b[24]) . the pll output frequency range (f sysclk ) is constrained to the range of 2. 4 ghz f sysclk 2.5 ghz by the internal vco . vco calibration when using the pll to generate the system clock, vco calibration is required to tune the vco appropriatel y and achieve good performance. when the reference input signal is stable, the vco c al enable bit in the cfr1 register, 0x00 [24] , must be asserted. subsequent vco calibra tions require that the vco calibration bit be cleared prior to initiating another vco calibration. vco calibration must occur before dac calibration to ensure optimal performance and functionality. ref_clk ref_clk 2 7 2 loop_filter 58 doubler enable cfr3[19] 55 54 doubler clock edge cfr3[16] 2 1, 2, 4, 8 enable in pll enable cfr3[18] loop filter pll out 0 1 0 1 sysclk input divider reset cfr3[22] input divider ratio cfr3[21:20] charge pump divide n cfr3[15:8] i cp cfr3[5:3] 10836-028 termin a tion ref_clk differentia l source, differentia l input single-ended source, differentia l input single-ended source, single-ended input 55 54 0.1f 0.1f pecl, l vpecl, or l vds driver ref_clk 55 54 50? 0.1f 0.1f balun (1:1) ref_clk ref_clk ref_clk ref_clk 55 54 0.1f 0.1f 50? 10836-029
ad9914 data sheet rev. c | page 22 of 48 pll charge pump /total feedback divider the charge pump current (i cp ) value is automatically chosen via the vco calibration process and n value (n = 10 to 255) stored in feedback divider n[7:0] in the cfr3 register (0x 02[15:8]) . n values below 10 should be avoided. note that t he total pll multiplication value for the pll is always 2n due to the fixed divide by 2 element in the feedback path. this is shown in figure 34. this fixed divide by 2 element forces only even pll multiplication. to manually override the charge pump current value, the manual i cp selection bit in cfr3 (0x02[6]) must be set to logic 1. this provides the user with additional flexibility to optimize the pll performance. table 7 lists the bit settings vs. the nominal charge pump current. table 7 . pll charge pump current i cp bits (cfr3[5:3 ]) charge pump current, i cp ( a) 000 125 001 250 010 375 011 500 (default) 100 625 101 750 110 875 111 1000 table 8. n divider vs . charge pump current n divider range recommended charge pump current, i cp ( a) 10 to 15 125 16 to 23 250 24 to 35 375 36 to 43 500 44 to 55 625 56 to 63 750 64 to 79 875 80 to 100 1000 pll loop filter components the loop filter is mostly internal to the device , as shown in figure 34. the recommended external capacitor value is 560 p f . because c p and r pz are integrated, it i s not recommended to adjust the loop bandwidth via the external capacitor value. the better option is to adjust the charge pump current even though it is a co arse adjustment. for example, suppose the pll is manually programmed such that i cp = 375 a, k v = 60 mhz/v, and n = 25 . this p roduces a loop bandwidth of approximately 250 k h z. figure 34 . ref clk pll external loop filter pll lock indication when the pll is in use, the pll lock bit (0x1b[24]) provides an active high indication that the pll has locked to the ref clk input signal. output shift keying (osk) the osk function (see figure 35 ) allows the user to control the output signal amplitude of the dds. the amplitude data generated by the osk block has priority over a ny other functional block that is programmed to deliver amplitude data to the dds. therefore, the osk data source, when enabled, overrides all other amplitude data sources. the operation of the osk function is governed by two cfr1 register bits , osk enable (0x00[8]) and external osk enable (0x0 0 [9]) , the ext ernal osk pin, the profile pins, and the 12 bits of amplitude scale factor found in one of eight profile registers . the profile pins are used to select the profile register containing the desired amplitude scale factor. the primary control for the osk block is the osk e nable bit (0x00[8]) . when the osk function is disabled, the osk input controls and osk pin are ignored. t he osk pin functionality dep ends on the stat e of the external osk enable bit and the osk enable bit . when both bit s are set to logic 1 and the osk pin is logic 0, the output amplitude is forced to 0; otherwise, if the osk pin is logic 1, the output amplitude is set by t he a mplitude scale factor valu e in one of eight profile registers depending on the profile pin selection. figure 35 . osk block diagram pfd cp loop_filter vco n 2 pll out pll in refclk pll r pz (3.5k?) c z = 560pf (recommended) 59 58 10836-030 ref 0.47f c p 50pf osk enable external osk enable 12 osk dds clock 12 ps0 ps1 ps2 25 26 27 66 to dds amplitude control parameter osk controller amplitude scale factor (1 of 8 selected profile registers [27:16]) 10836-031
data sheet ad9914 rev. c | page 23 of 48 digital ramp generat or (drg) drg overview to sweep phase, frequency, or amplitude from a defined start point to a defined endpoint, a completely digital ramp generator is included in the ad9914 . the drg makes use of eight control registe r bits, three external pins, and five 32 - bit re gisters (see figure 36). figure 36 . digital ramp block diagram the primary control for the drg is the digital ramp enable bit (0x01[19]) . when disabled, the other drg input controls are ignored and the internal clocks are shut down to conserve power. the output of the drg is a 32 - bit unsigned data bus that can be routed to any one of the three dds signal control parameters, as controlled by the two digital ramp destination bi ts in control function register 2 according to tabl e 9 . the 32 - bit output bus is msb - aligned with the 32 - bit frequency parameter, the 16 - bit phase parame ter, or the 12 - bit amplitude parameter, as defined by the destination bits. when the destinat ion is phase or amplitude, the unused lsbs are ignored. table 9 . digital ramp destination digital ramp destination bits (cfr2[21:20]) dds signal control parameter bits assigned to dds parameter 00 frequency 31:0 01 phase 31:18 1x 1 amplitude 31:20 1 x = d ont care. the ramp characteristics of the drg are fully programmable. this includes the upper and lower ramp limits, and independent control of the step size and step rate for both the positive and negative slope characteristics of the ramp. a detailed block diagram of the drg is shown in figure 37. the direction of the ramping function is controlled by the drctl pin. logic 0 on this pin causes the drg to ramp w ith a negative slope, whereas logic 1 causes the drg to ramp with a positive slope. the drg also supports a hold feature controlled via the drhold pin. when this pin is set to logic 1, the drg is stalled at its last state; otherwise, the drg operates normally. the dds signal control parameters that are not the destination of the d rg are taken from the active profile. figure 37 . digital ramp generator detail drct l dds clock drhold drover digi t al ram p enable load lrr a t i/o_upd a te clear digi t al ram p accumul a t or au t oclear digi t al ram p accumul a t or 32 32 digi t al ram p destin a tion 2 digi t al ram p no-dwel l 2 32 32 63 64 65 32 32 to dds signal control parameter digital ramp generator digital ramp lower limit register rising digital ramp step size register digital ramp upper limit register falling digital ramp step size register digital ramp rate register 10836-032 dds clock d q r lower limit 0 1 decrement ste p size preset q drct l load clear digi t a l ram p accumul a t or au t oclear digi t a l ram p acc . no dwel l limit contro l digi t a l ram p accumul a t or increment ste p size 32 32 0 1 neg a tive slope r a te positive slope r a te 16 16 32 16 63 drhold 64 32 32 load contro l logic load lrr a t i/o_upd a te digi t al ram p timer accumul a t or reset contro l logic no-dwel l contro l 2 32 32 t o dds signa l contro l p arameter upper limit 32 10836-033
ad9914 data sheet rev. c | page 24 of 48 drg slope control the core of the drg is a 32 - bit accumulator clocked by a programmable timer. the time base for the timer is the dds clock, which operates at 1/24 f sysclk . the timer establishes the interval between successive updates of the accumulator. the positive (+ t) and negative (? t) slope step intervals are independently programmable as given by sysclk f p t 24 = ? + sysclk f n t 24 = ? ? w here p and n are the two 16 - bit values stored in the 32 - bit digital ramp rate register and control the step interval. n defines the step interval of the negative slope portion of the ramp. p defines t he step interval of the positive slope portion of the ramp. the step size of the positive (step p ) and negative (step n ) slope portions of the ramp are 32 - b it values programmed into the 32 - bit rising and falling digital ramp step size register s (0x06 and 0x0 7) . program each of the step sizes as an unsigned integer (the hardware automatically interprets step n as a negative value). the relationship between the 32 - bit step size values and actual units of frequency, phase, or amplitude depend on the digital ramp destination bits. calculate the actual frequency, phase, or amplitude step size by substituting step n or step p for m in the following equations as required: sysclk f m step frequency ? ? ? ? ? ? = 32 2 31 2 m step phase = (radians) 29 2 45 m step phase = (degrees) fs i m step amplitude ? ? ? ? ? ? = 32 2 note that the frequency units are the same as those used to represent f sysclk (mhz, for example). the amplitude units are the same as those used to represent i fs , the full - scale output current of the dac (ma, for example). the phase and amplit ude step size equations yield the average step size. although the step size accumulates with 32 - bit precision, the phase or amplitude destination exhibits only 1 6 bits or 12 bits, respectively. therefore, at the destination, the actual phase or amplitude step is the accumula ted 32 - bit value truncated to 16 bits or 12 bits, respectively. as described previously, the step interval is controlled by a 16- bit programmable timer. there are three events that can cause this timer to be reloaded prior to its expiration. one event occurs when the digital ramp enable bit transitions from cleared to set, followed by an i/o update. a second event is a change of state in the drctl pin. the third event is enabled using the load lrr at i/o update bit (0x00[15]) . drg limit control the ramp accumulator is followed by limit control logic that enforces an upper and lower boundary on the output of the ramp generator. under no circumstances does the output of the drg exceed the programmed limit values while the drg is enabled. the limits are set through the 64 - bit digi tal ramp limit register. note that the upper limit value must be greater than the lower limit value to ensure normal operation. drg accumulator clear the ramp accumulator can be cleared (that is, reset to 0) under program control. when the ramp accumulator is cleared, it forces the drg output to the lower limit programmed into the digital ramp limit register. with the limit control block embedded in the feedback path of the accumulator, resetting the accumulator is equivalent to presetting it to the lower l imit value.
data sheet ad9914 rev. c | page 25 of 48 figure 38 . normal ramp generation normal ramp generation normal ramp generation implies that both no - dwell bits are cleared (see the no - dwell ramp generation section for details). in figure 38 , a sample ramp wavefo rm is depicted with the required control signals. the top trace is the drg output. the next trace down is the status of the drover output pin (assuming that the drg over output enable bit is set). the remaining traces are control bits and control pins. the pertinent ramp parameters are also identified (upper and lower limits plus step size and t for the positive and negative slopes). along the bottom, circled numbers identify specific events. these events are referred to by number (event 1 and so on) in th e following paragraphs. in this example, the positive and negative slopes of the ramp are different to demonstrate the flexibility of the drg. the parameters of both slopes can be programmed to make the positive and negative slopes the same. event 1 the di gital ramp enable bit is set, which has no effect on the drg output because the bit is not effective until an i/o update occurs . event 2 an i/o update registers the digital ramp enable bit. if drctl = 1 is in effect (the gray portion of the drctl trace), t he drg output immediately begins a positive slope (the gray portion of the drg output trace). otherwise, if drctl = 0, the drg output is initialized to the lower limit. event 3 drctl transitions to logic 1 to initiate a positive slope at the drg output. in this example, the drctl pin is held long enough to cause the drg to reach its programmed upper limit. the drg remains at the upper limit until the ramp accumulator is cleared ( drctl = 0 ) or the upper limit is reprogrammed to a higher value. in the latter case, the drg immediately resumes its previous positive slope profile. event 4 drctl transitions to logic 0 to initiate a negative slope at the drg output. in this example, the drctl pin is held long enough to cause the drg to reach its programmed lower l imit. the drg remains at the lower limit until drctl = 1, or until the lower limit is reprogrammed to a lower value. in the latter case, the drg immediately resumes its previous negative slope profile. event 5 drctl transitions to logic 1 for the second ti me, initiating a second positive slope. event 6 the positive slope profile is interrupted by drhold transitioning to logic 1. this stalls the ramp accumulator and freezes the drg output at its last value. event 7 drhold transitions to logic 0, releasing th e ramp accumulator and reinstating the previous positive slope profile. event 8 the clear digital ramp accumulator bit is set, which has no effect on the drg because the bit is not effective until an i/o update is issued. event 9 an i/o update registers th at the clear digital ramp accumulator bit is set, resetting the ramp accumulator and forcing the drg output to the programmed lower limit. the drg output remains at the lower limit until the clear condition is removed. event 10 the clear digital ramp accum ulator bit is cleared, which has no effect on the drg output because the bit is not effective until an i/o update is issued. event 11 an i/o update registers that the clear digital ramp accumulator bit is cleared, releasing the ramp accumulator; and the pr evious positive slope profile restarts. event 12 the autoclear digital ramp accumulator bit is set, which has no effect on the drg output because the bit is not effective until an i/o update is issued. drg output lower limit upper limit drct l drhold au t oclear digi t a l ram p accumul a t or clear digi t a l ram p accumul a t or i/o_upd a te positive ste p size neg a tive ste p size p dds clock cycles n dds clock cycles 1 dds clock cycle digi t a l ram p enable drover clear release au t o clear C t + t 1 2 3 4 5 6 7 8 9 10 1 1 12 13 10836-034
ad9914 data sheet rev. c | page 26 of 48 event 13 an i/o update registers that the autoclear digital ramp accumulator bit is set, resetting the ramp accumulator. however, with an automatic clear, the ramp accumulator is held in reset for only a single dds clock cycle. this forces the drg output to the lower limit, but the ramp accumulator is imme di - ately made available for normal operation. in this example, the drctl pin remains logic 1; therefore, the drg output restarts the previous positive ramp profile. no - dwell ramp generation the two no - dwell high and no - dwell low bits (0x01[18:17]) in cfr 2 add to the flexibility of the drg capabilities. during normal ramp generation, when the drg output reaches the programmed upper or lower limit, it simply remains at the limit until the operating parameters dictate otherwise. however, during no - dwell operat ion, the drg output does not necessarily remain at the limit. for example, if the digital ramp no - dwell high bit is set when the drg reaches the upper limit, it automatically (and immediately) snaps to the lower limit (that is, it does not ramp back to the lower limit; it jumps to the lower limit). likewise, when the digital ramp no - dwell low bit is set, and the drg reaches the lower limit, it automatically (and immediately) snaps to the upper limit. during no - dwell operation, the drctl pin is monitored for state transitions only; that is, the static logic level is immaterial. during no - dwell high operation, a positive transition of the drctl pin initiates a positive slope ramp, which continues uninterrupted (regardless of any further activity on the drctl p in) until the upper limit is reached. during no - dwell low operation, a negative transition of the drctl pin initiates a negative slope ramp, which continues uninterrupted (regardless of any further activity on the drctl pin) until the lower limit is reache d. setting both no - dwell bits invokes a continuous ramping mode of operation; that is, the drg output automatically oscillates between the two limits using the programmed slope parameters . furthermore, the function of the drctl pin is slightly different . i nstead of controlling the initiation of the ramp sequence, it only serves to change the direction of the ramp; that is, if the drg output is in the midst of a positive slope and the drctl pin transitions from logic 1 to logic 0 , the drg imme diately switch es to the negative slope parameters and resumes oscilla - tion between the limits. likewise, if the drg output is in the midst of a negative slope and the drctl pin transitions from logic 0 to logic 1, the drg immediately switches to the positive slope param eters and resumes oscillation between the limits. when both no - dwell bits are set, the drover signal produces a positive pulse (two cycles of the dds clock) each time the drg output reaches either of the programmed limits (assuming that the dr g over output enable bit (0x01[13] ) is set). a no - dwell high drg output waveform is shown in figure 39 . the waveform diagram assumes that the digital ramp no - dwell high bit is se t and has been registered by an i/o update. the status of the drover pin is also shown with the assumption that the drg over output enable bit has been set. the circled numbers in figure 39 indicate specific events, which are explained as follows: event 1 indicates the instant that an i/o update registers that the digital ramp enable bit is set. event 2 drctl transitions to logic 1, initiating a positive slope at the drg output. event 3 drctl transition s to logic 0, which has no effect on the drg output. event 4 because the digital ramp no - dwell high bit is set, the moment that the drg output reaches the upper limit, it imme - diately switches to the lower limit, where i t remains until the next logic 0 to logic 1 transition of drctl. event 5 drctl transitions from logic 0 to logic 1, which restarts a positive slope ramp. event 6 and event 7 drctl transitions are ignored until the drg output reaches the programmed upper li mit. event 8 because the digital ramp no - dwell high bit is set, the moment that the drg output reaches the upper limit, it immedi - ately switches to the lower limit, where it remains until the next logic 0 to logic 1 transition of drctl. operation with the digital ramp no - dwell low bit set (instead of the digital ramp no - dwell high bit) is similar, except that the drg output ramps in the negative direction on a logic 1 to logic 0 transition of drctl and jumps to the upper limit upon reachi ng the lower limit. figure 39 . no - dwell high ramp generation upper limit p dds clock cycles 1 2 3 4 5 6 7 8 drg output lower limit drct l positive ste p size drover + t 10836-035
data sheet ad9914 rev. c | page 27 of 48 drover pin the drover pin provides an external signal to indicate the status of the drg. specifically, when the d rg output is at either of the programmed limits, the drover pin is logic 1; otherwise, it is logic 0. in the special case of both no - dwell bits set, the drover pin pulses positive for two dds clock cycles each time the drg output reaches either of the prog rammed limits. frequency jumping capability in drg mode another feature of the ad9914 allows the user to s kip a predefined range of frequencies during a normal sweep . the frequency jump enable bit in cfr2 (0x01 [ 14] ) enable s this functio nality. when this bit is set , the sweeping logic monitor s the instantaneous frequency. when it reaches the frequency point defined in the l ower f requency j ump r egister (0x09) on the next accumulation cycle, instead o f accumulating a delta tuning word as in normal sweepi ng, it skip s directly to the frequency value set in the u pper f req uency jump r egister (0x0a) , and vice versa. figure 40 shows how this feature works. a second frequency jump can also be allowed if the f req uency j ump r egisters are reprogrammed before the sweeping is complete. the following r ules apply when this feature is enabled . ? the frequency jump values must lie between the low er limit and upper limit of the frequency sweep range . ? the l ower f requency jump register value must be lower than that of the u pper f requency jump register value . figure 40 . frequency vs. time power - down control the ad9914 offers the ability to independently power down three specific sections of the device. power - down functionality applies to the following: ? digital core ? dac ? input ref clk clock circuitry a power - down of the digital core disables t he ability to update the serial /parallel i/o port. however, the digital power - down bit (0x00[7]) can still be cleared to prevent the possi bility of a non recoverable state. software power - down is controlled via three independent power - down bits in cfr1. software control requires that the ext_pwr_dwn pin be forced to a logic 0 state. in this case, setting the desired power - down bits ( 0x00[7:5] ) via the se rial i/o port powers down the associated functional block, whereas clearing the bits restores the function. alternatively, all three functions can be simultaneously powered down via external hardware control through the ext_pwr_dwn pin . when this pin is fo rced to logic 1, all four circuit blocks are powered down regardless of the state of the power - down bits; that is, the independent power - down bits in cfr1 are ignored and overridden when ext_pwr_dwn is logic 1. based on the state of the external power - down control bit, the ext_pwr_dwn pin produces either a full power - down or a fast recovery power - down. the fast recovery power - down mode maintains power to the dac bias circuitry and the pll, vco, and input clock circuitry. although the fast recovery power - dow n does not conserve as much power as the full power - down, it allows the device to awaken very quickly from the power - down state. frequency t upper limit 0x09 0x0a lower limit 10836-036
ad9914 data sheet rev. c | page 28 of 48 programming and function p ins the ad9914 is equipped with a 32 - bit parallel port. the 32 - bit port is for programming the internal registers of the device in either serial mode or parallel mode as well as allow ing for direct modulation control of f requency (ftw) , p hase (pow), and amplitude (amp) . the state of the external function pins (f0 to f3) determine s how the 32 - bit parallel port is configured . pin 28 to pin 31 are the function pins. refer to tabl e 10 for possible configurations. note that t he osk enable bit, cfr1[8] , must be set to enable amplitude control , as shown in table 10. table 10 . parallel port configurations function pins , 32- bit parallel port pin assignment f[ 3:0 ] 1 mode description bits [ 31:24 ] 2 bits [ 23:16 ] 3 bits [ 15:8 ] 4 bits [ 7:0 ] 5 0000 parallel programming mode data [ 15:8] ( o ptional) data [ 7:0] address [ 7:0] used to control writes, reads, and 8- bit or 16- bit data - word . see the parallel programming section for details. 0001 serial p rogramming mode not u sed not u sed not used used to control sclk, sdio, sdo, cs , and sync io . see the serial programming section for details. 0010 full 32 bits of d irect frequency tuning word control. msb and lsb aligned to parallel port pin s ftw [ 31:24] ftw [ 23:16] ftw [ 15:8] ftw [ 7:0] 0011 full 32 bits of d irect frequency tuning word control with different parallel port pin assignment s ftw [ 15:8] ftw [ 7:0] ftw [ 31:24] ftw [ 23:16] 0100 full 16 bits of d irect phase offset control and full 12 bits of direct amplitude control pow [ 15:8] pow [ 7:0] amp [ 11:8] amp [ 7:0] 0101 full 12 bits of direct amplitude control and full 16 bits of direct phase offset control amp [ 11:8] amp [ 7:0] pow [ 15:8] pow [ 7:0] 0110 24 bits of p artial ftw control and 8 bits of partial a mplitude control ftw [ 31:24] ftw [ 23:16] ftw [ 15:8] amp [ 15:8] 0111 24 bits of partial ftw control and 8 bits of partial phase offset control ftw [ 31:24] ftw [ 23:16] ftw [ 15:8] pow [ 15:8] 1000 24 bits of partial ftw control and 8 bits of partial amplitude control ftw [ 31:24] ftw [ 23:16] ftw [ 15:8] amp [ 7:0] 1001 24 bits of partial ftw control and 8 bits of partial phase offset control ftw [ 31:24] ftw [ 23:16] ftw [ 15:8] pow [ 7:0] 1010 24 bits of partial ftw control and 8 bits of partial amplitude control ftw [ 23:16] ftw [ 15:8] ftw [ 7:0] amp [ 15:8] 1011 24 bits of partial ftw control and 8 bits of partial phase offset control ftw [ 23:16] ftw [ 15:8] ftw [ 7:0] pow [ 15:8] 1100 24 bits of partial ftw control and 8 bits of partial amplitude control ftw [ 23:16] ftw [ 15:8] ftw [ 7:0] amp [ 7:0] 1101 24 bits of partial ftw control and 8 bits of partial phase offset control ftw [ 23:16] ftw [ 15:8] ftw [ 7:0] pow [ 7:0] 1110 not u sed not u sed not u sed not u sed 1111 not u sed not u sed not u sed not u sed 1 pin 31 to pin 28. 2 pin 68 to pin 72, pin 75 to 77 . 3 pin 78 to pin 81, pin 87, pin 88, pin 1 , pin 2 . 4 pin 3 to pin 5, pin 8 to pin 12 . 5 pin 13 to pin 15, pin 18 to pin 22 .
data sheet ad9914 rev. c | page 29 of 48 figure 41 . parallel port block diagram the 32 - pin parallel port of the ad9914 works in conjunction with an independent set of four function pins that control the functionality of the parallel port. the 32 pins of the parallel port constitute a 32 - bit word designated by bits [31:0] (31 indicating the most significant bit (msb) and 0 indicating the least significant bit (lsb)) , with the four function pins designated as f[3:0]. the relationship between the function pins, the 32 - pin parallel port, the internal programming registers, and the dds control parameters (frequency, phase, and amplitude) is illustrated in figure 41 . note that the parallel port operates in three different modes as defined by the function pins. the p arallel m ode is in effect when the logic levels applied to the function pins are f[3:0] = 0000. th is allows the parallel port to function as a parallel interface providing access to all of the device programming registers. in p arallel mode, the 32 - pin port ( bits [31:0]) is subdivided into three groups with bits [31:16] constituting 16 data bits, bits[15: 8] constituting eight address bits, and bits[2:0] constituting three control bits. the address bits target a specific device register, whereas the data bits co nstitute the register content. the control bits establish read or write functionality as well as set the width of the data bus. that is, the user can select whether the data bus spans 16 bits ( bits [31:16]) or eight bits ( bits [23:16]). the p arallel m ode allows the user to write to the device registers at rates of up to 200 mb p s using 16 - bit data (or 100 mb p s using 8 - bit data). the s erial m ode is in effect when the logic levels applied to the function pins are f[3:0] = 0001. this allows the parallel port to function as a serial interface providing access to all of the device prog ramming registers. in this mode, only five pins of the 32 - pin parallel port are functional ( bits [4:0]). these pins provide chip select ( cs ), serial clock (sclk), and i/o synchronization (syncio) functionality for the serial interface, as well as two serial data lines (sdo and sdio). the s erial m ode supports data rates of up to 80 mb p s. when the logic levels applied to the function pins are f[3:0] = 0010 to 1101 (note that 1110 and 1111 are unused), the parallel port functions as a high spe ed interface with direct access to the 32- bit frequency, 16 - bit phase , and 12 - bit amplitude parameters of the dds core. the table in figure 41 shows the segmentation of the 32 - pin parallel port by identifying bits [31:0] with the frequency (ftw[31:0]), phase (pow[15:0]) , and amplitude (amp[15:0]) parameters of the dds. note, however, that although amp[15:0] indicate 16 - bit resolution, the actual amplitude resolution is 12 bits. therefore , only amp[11:0] provide amplitude control (that is, amp[15:12] are not used). parallel port pins 4 decode d q ck 32 routing logic 32 32 32 27 8 8 8 wr rd direct modes 5 sdo syncio sdio sclk cs parallel mode serial mode ftw frequency phase amplitude dds 32 16 12 pow amp 0000 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 0001 0010 parallel mode serial mode direct mode osk enable 10836-046 notes 1. amp[11:0] controls amplitude. amp[15:12] unused. function pins function pins and direct mode bits[31:0] vs. ftw, pow, amp f[3:0] bits[31:0] f[3:0] bits[31:24] bits[23:16] bits[15:8] bits[7:0] ftw[31:24] ftw[15:8] pow[15:8] amp[11:8] ftw[31:24] ftw[31:24] ftw[31:24] ftw[31:24] ftw[23:16] ftw[23:16] ftw[23:16] ftw[23:16] ftw[23:16] ftw[7:0] pow[7:0] amp[7:0] ftw[23:16] ftw[23:16] ftw[23:16] ftw[23:16] ftw[15:8] ftw[15:8] ftw[15:8] ftw[15:8] ftw[15:8] ftw[31:24] amp[11:8] pow[15:8] ftw[15:8] ftw[15:8] ftw[15:8] ftw[15:8] ftw[7:0] ftw[7:0] ftw[7:0] ftw[7:0] ftw[7:0] ftw[23:16] amp[7:0] pow[7:0] amp[15:8] pow[15:8] amp[7:0] pow[7:0] amp[15:8] pow[15:8] amp[7:0] pow[7:0] programming registers io_update bit 4 bit 3 bit 2 bit 1 bit 0 serial control system clock sync_clk parallel control bits[31:24] bits[23:16] bits[15:8] bit 2 bit 1 bit 0 d[15:8] d[7:0] a[7:0] 16 bits/8 bits
ad9914 data sheet rev. c | page 30 of 48 furthermore, to make use of amplitude control, the user must be sure to program the osk e nable bit in the cfr1 register (0x00[8]) to logic 1. the combination of the f[3:0] pins and bits [31:0] provides the ad9914 with unprecedented modulation capability by allowing the user direct control of the dds parameters (frequency, phase, amplitud e, or various combinations thereof). furthermore, the parallel port operates at a sample rate equal to 1/24 of the system sample clock. this allows for updates of the dds parameters at rates of up to 145 msps (assuming a 3.5 ghz system clock) allowing the ad9914 to acc ommodate applications with wide band modulation requirements. be aware that the frequency, phase , and amplitude changes applied at the parallel port travel to the dds core over different paths , exper iencing different propagation times (latency). therefore , modulating more than one dds parameter necessitates setting the devices m atched l atency enable bit in the cfr2 register (0x01[15]) , which equalizes the latency of each dds parameter as it propagate s from the parallel port to the dds core. note that high speed modulation require s a dac reconstruction filter with sufficient bandwidth to accommodate the instantaneous time domain transitions. because direct access to the dds parameters occurs via the ft w, pow , and amp registers, the io_update pin (see figure 41 ) adds another layer of flexibility. to accommodate this functionality, the ad9914 provides a register control bit, p arallel p ort s t reaming enable (0x00[17]) . when this bit is set to logic 1, the parallel port operates without the need for an i/o update . when this bit is logic 0, however, the device delivers the parallel port data to the appropriate registers (ftw, pow, amp), but not to the dds core. data does not transfer to the dds core until the user asserts the io_update pin. for example , suppose that an application requires frequency and amplitude modulation with full 32 - bit frequency resolution and full 12 - bit amplitude resolutio n. note that none of the f[3:0] pin combinations supports such modulation capability directly. to circumvent this problem, set the p arallel p ort s treaming enable bit (0x00[17]) to logic 0. this allows for the use of two d irect m ode cycles of the 32 - pin par allel port, each with a different function pin setting, without affecting the dds core until assertion of the io_update pin. that is, during the first d irect m ode cycle, set the function pins to f[3:0] = 0010, which routes all 32 bits to the ftw register ( frequency). on the next d irect m ode cycle , set the function pins to f[3:0] = 0100, which provides full 12 - bit access to the amp register (amplitude). be aware, however, this also provides acc ess to the pow register (phase); therefore, be sure keep the phase bits static. next, toggle the io_update pin, which synchronously transfers the new frequency and phase values from the ftw and pow registers to the dds core. this mode of operation reduces the overall modulation rate by a factor of t hree because it requires two separate operations on the parallel port followed by an io_update . however, this still allows for modulation sample rates as high as ~49 msps .
data sheet ad9914 rev. c | page 31 of 48 serial programming to enabl e spi operations , s et pin 28 (f0) to logic hi gh and pin 29 to pin 31 (f1 to f3) to logic low . to program the ad9914 with a parallel interface , see th e parallel programming section. control interface serial i/o the ad9914 serial port is a flexible, synchronous serial commu - nications port allowing easy interface to many industry - standard microc ontrollers and microprocessors. the serial i/o is compatible with most synchronous transfer formats. the interface allows read/write access to all registers that configure the ad9914 . msb - first or lsb - first transfer formats are supported. in addition, the serial interface port can be configured as a single pin input/output (sdio) allowing a 2 - wire interface, or it can be configured as two unidirectional pins for input/ output (sdio and sdo) , enabling a 3 - wire interface. two optional pins (i/o_sync and cs ) enable greater flexibility for designing systems with the ad9914 . table 11. serial i/o pin description pin n o. mnemonic serial i/o description 18 d4/sync io syncio 19 d3 /sdo sdo 20 d2/sdio/ wr sdio 21 d1 /sclk / rd sclk 22 d0 / cs /pwd cs c hip s elect general serial i/o o peration there are two phases to a serial communications cycle. the first is the instruction phase to write the instruction byte into the ad9914 . the instruction byte contains the address of the register to be accessed and defines whether the upcoming data transfer is a write or read operation. for a write cycle, phase 2 represents t he data transfer between the serial port controller to the serial port buffer. the number of bytes transferred is a function of the register being accessed. for example, when accessing control function register 2 (address 0x01), phase 2 requires that four bytes be transferred. each bit of data is registered on each corresponding rising edge of sclk. the serial port controller expects that all bytes of the register be accessed; otherwise, the serial port controller is put out of sequence for the next communi cation cycle. however, one way to write fewer bytes t han required is to use the sync io pin feature. the syncio pin function can be used to abort an i/o operation and reset the pointer of the serial port con troller. after a syncio, the next byte is the instruction byte. note that every com pleted byte written prior to a syncio is preserved in the serial port buffer. partial bytes written are not preserved. at the completion of any communication cycle, the ad9914 serial port controller expects the next eight rising sclk edges to be the instruction byte for the next communi cation cycle. after a write cycle, the programmed data resides in the serial port buffer and is inactive. i/o_update transfer s data from the serial port buffer to active registers. the i/o update can be sent either after each communication cycle or when all serial operations are complete. in addition, a change in profile pins can initiate an i/o update. for a read cycle, phase 2 is the same as the write cycle with the following differences: data is read from the active registers, not the serial port buffer, and data is driven out on the falling edge of sclk. note that , to read back any profile register (0x0b to 0x1a ), the three e xternal profile pins must be used. for example, if the pro file register is profile 5 (0x15 ), the p s [0:2] pins must equal 101.this is not required to write to the profile registers. instruction byte the instruction byte contains the following information as shown in the instruction byte information bit map. instruction byte information bit map msb lsb i 7 i 6 i 5 i 4 i 3 i 2 i 1 i 0 r/ w x a5 a4 a3 a2 a1 a0 r/ w bit 7 of the instruction byte determines whether a read or write data transfer occurs after the instruction byte write. logic 1 indicates a read operation. logic 0 indicates a write operation. x bit 6 of the instruction byte is dont care . a5, a4, a3, a2, a1, a0 bit 5, bit 4, bit 3, bit 2, bit 1 , and bit 0 of the instruction byte determine which register is accessed during the data transfer portion of the communications cycle. serial i/o port pin descriptions sclk serial clock the serial clock pin is used to synchronize data to and from the ad9914 and to run the internal state machines. cs chip select bar cs is an active low input that allows more than one device on the same serial communications line . the sdo and sdio pins go to a high impedance state when this input is high. if driven high during any communications cycle, that cycle is suspended until cs is reactivated low. chip select ( cs ) can be tied low in syste ms that maintain control of sclk. sdio serial data input/output data is always written into the ad9914 on this pin. however, this pin can be used as a bidirectional data line. bit 1 of cfr1 ( 0x00 ) controls the configuration of this pin. the default is logic 0 , which configures the sdio pin as bidirectional.
ad9914 data sheet rev. c | page 32 of 48 sdo serial data out data is read from this pin for protocols that use separate lines for transmitting and receiving data. when the ad9914 operates in single bidirectional i/o mode, this pin does not output data and is set to a high impedance state. sync i o input/output reset sync i o synchronizes the i/o port state machines without affecting the contents of the addressable registers. an active high input on the sync io pin causes the current communica tion cycle to abort. after syncio returns low (logic 0), another communication cycle can begin, starting with the instruction byte write. i/o_update input/output update the i/o update initiates the transfer of written data from the serial or parallel i/o port buffer to active registers. i/o_update is active on the rising edge, and its pulse width must be greater than one sync_clk period. serial i/o timing di agrams figure 42 through figure 45 provide basic examples of the timing relationships between the various control signals of the serial i/o port. most of the bits in the register map are not transferred to their internal destina tions until assertion of an i/o update, which is not included in the timing diagrams that follow. note that the sclk stall condition between the instruction byte cycle and data transfer cycle in figure 42 to figure 45 i s not required. msb/lsb transfers the ad9914 serial port can support both most significant bit (msb) first or least significant bit (lsb) first data formats. this functionality is controlled by bit 0 in cfr 1 (0x00). the default format is msb first. if lsb first is active, all data, including the ins truction byte, must follow lsb - first conven tion. note that the highest number found in the bit range column for each register is the msb, and the lowest number is the lsb for that register . figure 42 . serial port write timing, clock stall low figure 43 . 3 - wire serial port read timing, clock stall low figure 44 . serial port write timing, clock stall high figure 45 . 2 - wire serial port read timing, clock stall high i 7 sdio instruction cycle d at a transfer cycle sclk cs i 6 i 5 i 4 i 3 i 2 i 1 i 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10836-037 d o7 instruction cycle dat a transfer cycle don't care i 7 i 6 i 5 i 4 i 3 i 2 i 1 i 0 sdio sclk cs sdo d o6 d o5 d o4 d o3 d o2 d o1 d o0 10836-038 i 7 sdio instruction cycle dat a transfer cycle sclk cs i 6 i 5 i 4 i 3 i 2 i 1 i 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10836-039 i 7 sdio instruction cycle d at a transfer cycle sclk cs i 6 i 5 i 4 i 3 i 2 i 1 i 0 d o7 d o6 d o5 d o4 d o3 d o2 d o1 d o0 10836-040
data sheet ad9914 rev. c | page 33 of 48 parallel programming (8 - /16- b it ) the state of the external function pins (f0 to f3) determine the type of interface used by the ad9914 . pin 28 to pin 31 are dedicated function pins. to enable the p arallel mode interface set pin 28 to pin 31 to logic low. parallel programming consist s of eight address lines and either eight or 16 bidirectional data lines for read/write operations. the logic state on pin 22 determines the width of the data lines used . a logic low on pin 22 sets the data width to eight bits , and logic high sets the data width to 16 bits. in addition, parallel mode h as dedicated write/read control inputs. if 16 - bit mode is used , the upper byte , bits [ 15:8 ] , goes to the addressed register and the lower byte , bits [ 7:0 ] , goes to the adjacent lower address. parallel i/o operation allows write access to each byte of any register in a single i/o op eration . readback capability for each register is included to ease designing with the ad9914 . table 12 . parallel port read timing (see figure 46) parameter value unit test conditions/comments t adv 92 n s max address to data valid time t ahd 0 ns min address hold time to rd signal inactive t rdlov 69 ns max rd low to output valid t rdhoz 50 ns max rd high to data three - state t rdlow 69 ns max rd signal minimum low time t rdhigh 50 ns max rd signal minimum high time table 13 . parallel port write timing (see figure 47) parameter value unit test conditions / comments t asu 1 ns address setup time to wr signal active t dsu 3.8 ns data setup time to wr signal active t ahd 0 ns address hold time to wr signal inactive t dhd 0 ns data hold time to wr signal inactive t wrlow 2.1 ns wr signal minimum low time t wrhigh 3.8 ns wr signal minimum high time t wr 10.5 ns minimum write time figure 46 . parallel port read timing diagram figure 47 . parallel port write timing diagram a1 d1 a2 d2 a3 d3 a[7:0] rd d[7:0] or d[15:0] t rdhoz t rdhigh t rdlow t rdlov t adv t ahd 10836-041 a1 a2 a3 d1 d2 d3 a[7:0] wr d[7:0] or d[15:0] 10836-042 t wr t asu t ahd t wrhigh t dhd t dsu t wrlow
ad9914 data sheet rev. c | page 34 of 48 register map and bit descriptions table 14. register map register name (serial address) bit range (parallel address) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) 1 cfr1 control function register 1 (0x00) [7:0] (0x00) digital power - down dac power - down ref clk input power - down open external power - down control open sdio input only lsb first mode 0x08 [15:8] (0x01) load lrr at i/o update autoclear digital ramp accumu - lator autoclear phase accumu - lator clear digital ramp accumulator clear phase accumulator open external osk enable osk enable 0x00 [23:16] (0x02) open parallel port streaming enable enable sine output 0x01 [31:24] (0x03) open vco c al enable 0x00 cfr2 control function register 2 (0x01) [7:0] (0x04) open 0x00 [15:8] (0x05) matched latency enable frequency jump enable drg over output enable open sync_clk enable sync_clk invert reserved open 0x09 [23:16] (0x06) profile mode enable parallel data port enable digital ramp destination digital ramp enable digital ramp no - dwell high digital ramp no - dwell low program modulus enable 0x00 [31:24] (0x07) open 0x00 cfr3 control function register 3 (0x02) [7:0] (0x08) open manual i cp selection i cp [2:0] lock detect enable minimum ldw[1:0] 0x1c [15:8] (0x09) feedback divider n[7:0] 0x19 [23:16] (0x0a) open input divider reset input divider[1:0] doubler enable pll enable pll r ef disable doubler clock edge 0x00 [31:24] (0x0b) open 0x00 cfr4 control function register 4 (0x03) [7:0] (0x0c) requires register default value settings (0x20) 0x20 [15:8] (0x0d) requires register default value settings (0x 2 1) 0x 2 1 [23:16] (0x0e) requires register default value settings (0x05) 0x05 [31:24] (0x0f) open auxiliary divider power - down dac cal clock power - down dac cal enable 2 0x00 digital ramp lower limit register (0x04) [7:0] (0x10) digital ramp lower limit[7:0] 0x00 [15:8] (0x11) digital ramp lower limit[15:8] 0x00 [23:16] (0x12) digital ramp lower limit[23:16] 0x00 [31:24] (0x13) digital ramp lower limit[31:24] 0x00
data sheet ad9914 rev. c | page 35 of 48 register name (serial address) bit range (parallel address) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) 1 digital ramp upper limit register (0x05) [7:0] (0x14) digital ramp upper limit[7:0] 0x00 [15:8] (0x15) digital ramp upper limit[15:8] 0x00 [23:16] (0x16) digital ramp upper limit[23:16] 0x00 [31:24] (0x17) digital ramp upper limit[31:24] 0x00 rising digital ramp step size register (0x06) [7:0] (0x18) rising digital ramp increment step size[7:0] n/a [15:8] (0x19) rising digital ramp increment step size[15:8] n/a [23:16] (0x1a) rising digital ramp increment step size[23:16] n/a [31:24] (0x1b) rising digital ramp increment step size[31:24] n/a falling digital ramp step size register (0x07) [7:0] (0x1c) falling digital ramp decrement step size[7:0] n/a [15:8] (0x1d) falling digital ramp decrement step size[15:8] n/a [23:16] (0x1e) falling digital ramp decrement step size[23:16] n/a [31:24] (0x1f) falling digital ramp decrement step size[31:24] n/a digital ramp rate register (0x08) [7:0] (0x20) digital ramp positive slope rate[7:0] n/a [15:8] (0x21) digital ramp positive slope rate[15:8] n/a [23:16] (0x22) digital ramp negative slope rate[7:0] n/a [31:24] (0x23) digital ramp negative slope rate[15:8] n/a lower frequency jump register (0x09) [7:0] (0x24) lower frequency jump point[7:0] 0x00 [15:8] (0x25) lower frequency jump point[15:8] 0x00 [23:16] (0x26) lower frequency jump point[23:16] 0x00 [31:24] (0x27) lower frequency jump point[31:24] 0x00 upper frequency jump register (0x0a) [7:0] (0x28) upper frequency jump point[7:0] 0x00 [15:8] (0x29) upper frequency jump point[15:8] 0x00 [23:16] (0x2a) upper frequency jump point[23:16] 0x00 [31:24] (0x2b) upper frequency jump point[31:24] 0x00 profile 0 (p0) frequency tuning word 0 register (0x0b) [7:0] (0x2c) frequency tuning word 0[7:0] 0x00 [15:8] (0x2d) frequency tuning word 0[15:8] 0x00 [23:16] (0x2e) frequency tuning word 0[23:16] 0x00 [31:24] (0x2f) frequency tuning word 0[31:24] 0x00
ad9914 data sheet rev. c | page 36 of 48 register name (serial address) bit range (parallel address) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) 1 profile 0 (p0) phase/ amplitude register (0x0c) [7:0] (0x30) phase offset word 0[7:0] 0x00 [15:8] (0x31) phase offset word 0[15:8] 0x00 [23:16] (0x32) amplitude scale factor 0[7:0] 0x00 [31:24] (0x33) open amplitude scale factor 0[11:8] 0x00 profile 1 (p1) frequency tuning word 1 register (0x0d) [7:0] (0x34) frequency tuning word 1[7:0] n/a [15:8] (0x35) frequency tuning word 1[15:8] n/a [23:16] (0x36) frequency tuning word 1[23:16] n/a [31:24] (0x37) frequency tuning word 1[31:24] n/a profile 1 (p1) phase/ amplitude register (0x0e) [7:0] (0x38) phase offset word 1[7:0] n/a [15:8] (0x39) phase offset word 1[15:8] n/a [23:16] (0x3a) amplitude scale factor 1[7:0] n/a [31:24] (0x3b) open amplitude scale factor 1[11:8] n/a profile 2 (p2) frequency tuning word 2 register (0x0f) [7:0] (0x3c) frequency tuning word 2[7:0] n/a [15:8] (0x3d) frequency tuning word 2[15:8] n/a [23:16] (0x3e) frequency tuning word 2[23:16] n/a [31:24] (0x3f) frequency tuning word 2[31:24] n/a profile 2 (p2) phase/ amplitude register (0x10) [7:0] (0x40) phase offset word 2[7:0] n/a [15:8] (0x41) phase offset word 2[15:8] n/a [23:16] (0x42) amplitude scale factor 2[7:0] n/a [31:24] (0x43) open amplitude scale factor 2[11:8] n/a profile 3 (p3) frequency tuning word 3 register (0x11) [7:0] (0x44) frequency tuning word 3[7:0] n/a [15:8] (0x45) frequency tuning word 3[15:8] n/a [23:16] (0x46) frequency tuning word 3[23:16] n/a [31:24] (0x47) frequency tuning word 3[31:24] n/a profile 3 (p3) phase/ amplitude register (0x12) [7:0] (0x48) phase offset word 3[7:0] n/a [15:8] (0x49) phase offset word 3[15:8] n/a [23:16] (0x4a) amplitude scale factor 3[7:0] n/a [31:24] (0x4b) open amplitude scale factor 3[11:8] n/a
data sheet ad9914 rev. c | page 37 of 48 register name (serial address) bit range (parallel address) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) 1 profile 4 (p4) frequency tuning word 4 register (0x13) [7:0] (0x4c) frequency tuning word 4[7:0] n/a [15:8] (0x4d) frequency tuning word 4[15:8] n/a [23:16] (0x4e) frequency tuning word 4[23:16] n/a [31:24] (0x4f) frequency tuning word 4[31:24] n/a profile 4 (p4) phase/ amplitude register (0x14) [7:0] (0x50) phase offset word 4[7:0] n/a [15:8] (0x51) phase offset word 4[15:8] n/a [23:16] (0x52) amplitude scale factor 4[7:0] n/a [31:24] (0x53) open amplitude scale factor 4[11:8] n/a profile 5 (p5) frequency tuning word 5 register (0x15) [7:0] (0x54) frequency tuning word 5[7:0] n/a [15:8] (0x55) frequency tuning word 5[15:8] n/a [23:16] (0x56) frequency tuning word 5[23:16] n/a [31:24] (0x57) frequency tuning word 5[31:24] n/a profile 5 (p5) phase/ amplitude register (0x16) [7:0] (0x58) phase offset word 5[7:0] n/a [15:8] (0x59) phase offset word 5[15:8] n/a [23:16] (0x5a) amplitude scale factor 5[7:0] n/a [31:24] (0x5b) open amplitude scale factor 5[11:8] n/a profile 6 (p6) frequency tuning word 6 register (0x17) [7:0] (0x5c) frequency tuning word 6[7:0] n/a [15:8] (0x5d) frequency tuning word 6[15:8] n/a [23:16] (0x5e) frequency tuning word 6[23:16] n/a [31:24] (0x5f) frequency tuning word 6[31:24] n/a profile 6 (p6) phase/ amplitude register (0x18) [7:0] (0x60) phase offset word 6[7:0] n/a [15:8] (0x61) phase offset word 6[15:8] n/a [23:16] (0x62) amplitude scale factor 6[7:0] n/a [31:24] (0x63) open amplitude scale factor 6[11:8] n/a profile 7 (p7) frequency tuning word 7 register (0x19) [7:0] (0x64) frequency tuning word 7[7:0] n/a [15:8] (0x65) frequency tuning word 7[15:8] n/a [23:16] (0x66) frequency tuning word 7[23:16] n/a [31:24] (0x67) frequency tuning word 7[31:24] n/a
ad9914 data sheet rev. c | page 38 of 48 register name (serial address) bit range (parallel address) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) 1 profile 7 (p7) phase/ amplitude register (0x1a) [7:0] (0x68) phase offset word 7[7:0] n/a [15:8] (0x69) phase offset word 7[15:8] n/a [23:16] (0x6a) amplitude scale factor 7[7:0] n/a [31:24] (0x6b) open amplitude scale factor 7[11:8] n/a usr0 (0x1b) [7:0] (0x6c) requires regis ter default value settings (0x00 ) 0x00 [15:8] (0x6d) requires register default value settings (0x08) 0x08 [23:16] (0x6e) requires register default value settings (0x00) 0x00 [31:24] (0x6f) open pll lock read only 1 a master reset is required after power up. the master reset returns the internal registers to their default values. 2 the dac cal enable bit must be manually set and then cleared after each power - up and every time ref clk or the internal system clock is changed. this initiates an internal calibration routine to optimize the setup and hold times for internal dac timing. failure to calibrate degrades ac performance or makes the part nonfunctional.
data sheet ad9914 rev. c | page 39 of 48 register bit descrip tions the serial i/o port registers span an address range of 0 to 27 (0x00 to 0x1b in hexadecimal notation ). this represents a total of 28 individual serial registers. if programming in parallel mode, the number of parallel registers increase s to 112 individual parallel registers . additionally, the registers are assigned n ames according to their functionality. in some cases, a register is given a mnemonic descriptor. for example, the register at serial address 0x00 is named control function register 1 and is assigned the mnemonic cfr1. this section provides a detailed descr iption of each bit in the ad9914 register map. for cases in which a group of bits serves a specific function, the entire group is considered a binary word and is described in aggregate. this section is organized in sequential order of the serial addresses of the registers. each subheading includes the register name and optional register mnemonic (in parentheses). also given is the serial address in hexadecimal format and the number of byt es assigned to the register. following each subheading is a table containing the individual bit descriptions for that particular register. the location of the bit(s) in the register is indicated by a single number or a pair of numbers separated by a colon; that is, a pair of numbers (a:b) indicates a range of bits from the most significant (a) to the least significant (b). for example, [ 5:2 ] implies bit position 5 to bit position 2, inclusive, with bit 0 identifying the lsb of the register. unless otherwise stated, programmed bits are not transferred to their inte rnal destinations until the assertion of the i/o_update pin or a profile pin change. control function register 1 (cfr1) address 0x00 table 15. bit description for cfr1 bits mnemonic description [31:25] open 24 vco c al enable 1 = initializes the auto internal pll calibration. the calibration is required if the pll is to provide the internal system clock. must first be reset to logic 0 before another calibration can be issued. [23:18] open open. 17 parallel port streaming enable 0 = the 32 bit parallel port needs an i/o update to activate or register any ftw, pow, or amp data presented to the 32 - bit parallel port. 1 = the parallel port continuously samples data on the 32 input pins using sync_clk and multiplexes the value of ftw/pow/amp accordingly, per the configuration of the f0 to f3 pins, without the need of an i/o update. data must meet the setup and hold times of the sync_clk rising edge. if the function pins are used dynamically to alter data between parameters, they must also meet the timing of the sync_clk edge. 16 enable sine output 0 = cosine output of the dds is selected . 1 = sine output of the dds is selected (default). 15 load lrr at i/o update ineffective unless cfr2[19] = 1. 0 = normal operation of the digital ramp timer (default). 1 = interrupts the digital ramp timer operation to load a new linear ramp rate (lrr) value any time i/o_update is asserted or a ps[2:0] change occurs. 14 autoclear digital ramp accumulator 0 = normal operation of the drg accumulator (default). 1 = the digital ramp accumulator is reset for one cycle of the dds clock (sync_clk), after which the accumula tor automatically resumes normal operation. as long as this bit remains set, the ramp accumulator is momentarily reset each time an i/o update is asserted or a ps[2:0] change occurs. this bit is synchronized with either an i/o update or a ps[2:0] change and the next rising edge of sync_clk. 13 autoclear phase accumulator 0 = normal operation of the dds phase accumulator (default). 1 = synchronously resets the dds phase accumulator anytime i/o_update is asserted or a profile change occurs. 12 clear digital ramp accumulator 0 = normal operation of the digital ramp generator (default). 1 = asynchronous, static reset of the drg accumulator. the ramp accumulator remains reset as long as this bit remains set. this bit is synchronized with either an i/o update or a ps[2:0] change and the next rising edge of sync_clk. 11 clear phase accumulator 0 = normal operation of the dds phase accumulator (default). 1 = asynchronous, static reset of the dds phase accumulator as long as this bit is set. this bit is synchronized with either an i/o update or a ps[2:0] change and the next rising edge of sync_clk. 10 open open.
ad9914 data sheet rev. c | page 40 of 48 bits mnemonic description 9 external osk enable 0 = manual osk enabled (default). 1 = automatic osk enabled. ineffective unless cfr1[8] = 1. 8 osk enable 0 = osk disabled (default). 1 = osk enabled. to engage any digital amplitude adjust using drg, profile, or direct mode via the 32 - bit parallel port, or osk pin, this bit must be set. 7 digital power - down this bit is effective without the need for an i/o update. 0 = clock signals to the digital core are active (default). 1 = clock signals to the digital core are disabled. 6 dac power - down 0 = dac clock signals and bias circuits are active (default). 1 = dac clock signals and bias circuits are disabled. 5 refclk input power - down this bit is effective without the need for an i/o update. 0 = refclk input circuits and pll are active (default). 1 = refclk input circuits and pll are disabled. 4 open open . 3 external power - down control 0 = assertion of the ext_pwr_dwn pin affects power - down . 1 = assertion of the ext_pwr_dwn pin affects fast recovery power - down. 2 open open . 1 sdio input only 0 = configures the sdio pin for bidirectional operation; 2- wire serial programming mode (default). 1 = configures the serial data i/o pin (sdio) as an input only pin; 3- wire serial programming mode. 0 lsb first mode 0 = configures the serial i/o port for msb - first format (default). 1 = configures the serial i/o port for lsb - first format. control function register 2 (cfr2) address 0x01 table 16 . bit descriptions for cfr2 bit(s) mnemonic description [31:24] open open . 23 profile mode enable 0 = disables profile mode functionality (default). 1 = enables profile mode functionality. profile pins are used to select the desired profile. 22 parallel data port enable see the parallel data port modulation mode section for more details. 0 = disables parallel data port modulation functionality (default). 1 = enables parallel data port modulation functionality. [21:20] digital ramp destination see table 9 for details. default is 00. see the digital ramp generator (drg) section for more details. 19 digit al ramp enable 0 = disables digital ramp generator functionality (default). 1 = enables digital ramp generator functionality. 18 digital ramp no - dwell high see the digital ramp generator (drg) section for details. 0 = disables no - dwell high functionality (default). 1 = enables no - dwell high functionality. 17 digital ramp no - dwell low see the digital ramp generator (drg) section for details. 0 = disables no - dwell low functionality (default). 1 = enables no - dwell low functionality. 16 programmable modulus enable 0 = disables programmable modulus. 1 = enables programmable modulus. 15 matched latency enable 0 = simultaneous application of amplitude, phase, and frequency changes to the dds arrive at the output in the order listed in table 2 under data latency (pipe line delay)(default). 1 = simultaneous application of amplitude, phase, and frequency changes to the dds arrive at the output simultaneously. 14 frequency jump enable 0 = disables frequency jump. 1 = enables frequency jump mode. must have the digital generator drg enabled for this feature. 13 drg over output enable 0 = disables the drover output. 1 = enables the drover output.
data sheet ad9914 rev. c | page 41 of 48 bit(s) mnemonic description 12 open open . 11 sync_clk enable 0 = the sync_clk pin is disabled and forced to a static logic 0 state; the internal clock signal continues to operate and provide timing to the data assembler. 1 = the internal sync_clk signal appears at the sync_clk pin (default). 10 sync_clk invert 0 = normal sync_clk polarity; q data associated with logic 1, i data with logic 0 (default). 1 = inverted sync_clk polarity. 9 reserved keep logic 0. [ 8:0] open open. control function register 3 (cfr3) address 0x02 table 17. bit descriptions for cfr3 bit(s) mnemonic description [31:23] open open . 22 input divider reset 0 = disables input divider reset function. 1 = initiates a input divider reset. [21:20] input divider divides the input ref clk signal by one of four values (1, 2, 4, 8). 19 doubler enable 0 = disables the doubler feature. 1 = enables the doubler feature. must have the doubler clock edge bit set to logic 1 to utilize this feature. 18 pll enable 0 = disables the internal pll. 1 = the internal pll is enabled and the output generates the system clock. the pll must be calibrated when enabled via vco calibration in register cfr1, bit 24. 17 pll r ef disable this bit should remain logic 0 (default). 16 doubler clock edge 0 = disables the internal doubler circuit. 1 = enables the doubler circuit. must have doubler enable bit set to logic 1 to utilize this feature. [15:8] feedback divider n the n divider value in bits[15:8] is one part o f the total pll multiplication available . the seco nd part is the fixed divide by two element in the feedback path . the refore, the total pll multiplication value is 2n. the valid n divider range is 10 to 255. the default n value for bits[15:8] = 25. this set s the tot al default pll multiplication to 50 or 2n. 7 open open . 6 manual i cp selection 0 = the internal charge pump current is chosen automatically during the vco calibration routine (default). 1 = the internal charge pump is set manually per table 7. [5:3] i cp manual charge pump current selection. see table 7. 2 lock detect enable 0 = disables pll lock detection. 1 = enables pll lock detection. [1:0] minimum ldw selects the number of ref clk cycles that the phase error (at the pfd inputs) must remain within before a pll lock condition can be read back via bit 24 in register 0x 00. 00 = 128 ref clk cycles 01 = 256 ref clk cycles 10 = 512 ref clk cycles 11 = 1024 re f clk cycles
ad9914 data sheet rev. c | page 42 of 48 control function register 4 (cfr4 ) address 0x0 3 table 18 . bit descriptions for dac bit(s) mnemonic description [31:27] open open 26 auxiliary divider power - down 0 = enables the sync out circuitry. 1 = disables the sync out circuitry 25 dac cal clock power - own 0 = enables the dac cal clock if bit 26 in register 0x03 is logic 0. 1 = disables the dac cal clock. 24 dac cal enable 1 = initiates an auto dac calibration. the dac cal calibration is required at power - up and any time the internal system clock is changed. [23:0] (see description) these bits must always be programmed with the default values listed in the default column in table 14. digital ramp lower limit register address 0x04 this register is effective only if the digital ramp enable bit in the cfr2 register (0x01 [19] ) = 1. see the digital ramp generator (drg) section for details. table 19. bit descriptions for digital ramp lower limit register bit(s) mnemonic description [31:0] digital ramp lower limit 32- bit digital ramp lower limit value. digital ramp upper limit register address 0x05 this register is effective only if the digital ramp enable bit in the cfr2 register (0x01[19]) = 1. see the digital ramp generator (drg) section for details. table 20. bit description s for digital ramp limit register bit(s) mnemonic description [31:0] digital ramp upper limit 32 - bit digital ramp upper limit value. rising digital ramp step size register address 0x06 this register is effective only if the digital ramp enable bit in the cfr2 register (0x01[19]) = 1. see the digital ramp generator (drg) section for details. table 21 . bit descriptions for rising digital ramp step size register bit(s) mnemonic description [31:0] rising digital ramp increment step size 32- bit digital ramp increment step size value. falling digital ramp step size register address 0x07 this register is effective only if the digital ramp enable bit in the cfr2 register (0x01[19]) = 1. see the digital ramp generator (drg) section for details. table 22 . bit descriptions for falling digital ramp step size register bit(s) mnemonic description [31:0] falling digital ramp decrement step size 32 - bit digital ramp decrement step size value.
data sheet ad9914 rev. c | page 43 of 48 digital ramp rate register address 0x0 8 this register is effective only if the digital ramp enable bit in the cfr2 register (0x01[19]) = 1. see the digital ramp generator (drg) section for details. table 23 . bit descriptions for digital ramp rate register bit(s) mnemonic description [31:16] digital ramp negative slope rate 16 - bit digital ramp negative slope value that defines the time interval between decrement values. [15:0] digital ramp positive slope rate 16- bit digital ramp positive slope value that defines the time interval between increment values. lower frequency jump register address 0x09 this register is effective only if the digital ramp enable bit (0x01[19]) = 1 and the frequency jump enable bit (0x01 [14] ) = 1 in the cfr2 register . see the digital ramp generator (drg) section for details. table 24 . bit descriptions for lower frequency jump register bit(s) mnemonic description [31:0] lower frequency jump point 32- bit digital lower frequency jump value. any time the lower frequency jump value is reached during a frequency sweep, the output frequency jumps to the upper frequency value instantaneously and continues frequency sweeping in a phase - continuous manner. upper frequency jump register address 0x0a this register is effective only if the digital ramp enable bit (0x01[19]) = 1 and the frequency jump enable bit (0x01[14]) = 1 in the cfr2 register. see the digital ramp generator (drg) section for details. table 25 . bit descriptions for upper frequency jump register bit(s) mnemonic description [31:0] upper frequency jump point 32- bit digital upper frequency jump value. any time the upper frequency jump value is reached during a frequency sweep, the output frequency jumps to the lower frequency value instantaneously and continues frequency sweeping in a phase - continuous manner.
ad9914 data sheet rev. c | page 44 of 48 profile registers there are 16 serial i/o addresses (address 0x 0b to address 0x01a ) de dicated to device profiles. e ig ht of the 16 profile s house up to eight single tone frequencies. the remaining eight profiles contain the corre sponding phase offset and amplitude parameters relative to the profile pin setting . to enable profile mode , set the profile mode enable bit in cfr2 (0x01 [23] ) = 1. t he active profile register is selected using the external p s [2:0] pins. profile 0 to profile 7, single tone registers 0x0b, 0x0d, 0x0f, 0x11, 0x13, 0x15, 0x17, 0x19 four bytes are assigned to each register. table 26. bit descriptions for profile 0 to profile 7 single tone r egister s bit(s) mnemonic description [31:0] frequency tuning word this 32 - bit number controls the dds frequency. profile 0 to profile 7, phase offset and amplitude registers 0x0c, 0x0e, 0x10, 0x12, 0x14, 0x16, 0x18, 0x1a four bytes are assigned to each register. table 27. bit descriptions for profile 0 to profile 7 phase offset and amplitude register s bit(s) mnemonic description [31:28] open open. [27:16] amplitude scale factor this 12 - bit word controls the dds frequency. note that the osk enable bit (0x00[8]) must be set to logic high to make amplitude adjustments. [15:0] phase offset word this 16 - bit word controls the dds frequency. usr 0 register address 0x1b table 28. bit descriptions for usr0 register bit(s) mnemonic description [31:25] open 24 pll lock this is a readback bit only. if logic 1 is read back, the pll is locked. logic 0 represents a nonlocked state. [23:0 ] (see description) these bits must always be programmed with the default values listed in the default column in table 14.
data sheet ad9914 rev. c | page 45 of 48 outline dimensions figure 48 . 88- lea d lead frame chip scale package [lfcsp_vq] 12 mm 12 mm body, very thin quad (cp - 88 - 5 ) dimensions shown in millimeters ordering guide parameter 1 temperature range package description package option ad9914bcpz ?40c to +85c 88 - lead lead frame chip scale package [lfcsp_vq] cp - 88 - 5 ad9914bcpz - reel7 ?40c to +85c 88- lead lead frame chip scale package [lfcsp_vq] cp -88-5 ad9914/pcbz evaluation board 1 z = rohs compliant part. * compliant t o jedec s t andards mo-220-vrrd except for minimum thickness and lead coun t . 07-02-2012-b 1 22 66 45 23 44 88 67 0.50 0.40 0.30 0.30 0.23 0.18 10.50 ref 0.60 max 0.60 max 6.70 ref sq 0.50 bsc 0.138~0.194 ref 12 max se a ting plane t o p view exposed pad bottom view 0.70 0.65 0.60 0.045 0.025 0.005 pin 1 indic a t or 12.10 12.00 sq 1 1.90 1 1.85 1 1.75 sq 1 1.65 pin 1 indic a t or * 0.90 0.85 0.75 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. coplanarit y 0.08
ad9914 data sheet rev. c | page 46 of 48 notes
data sheet ad9914 rev. c | page 47 of 48 notes
ad9914 data sheet rev. c | page 48 of 48 notes ? 2012 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10836 - 0 - 11/13(c)

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